S71GS256 datasheet(146/195 Pages) SPANSION

146 / 195 page

146

CellularRAM Type 2

cellRAM_00_A0 October 4, 2004

Advan ce

In form ati o n

tSP

Notes:

1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.

2. WAIT will assert LC + 1 or 2LC + 1 cycles for variable latency (depending upon refresh status).

Figure 47. Continuous Burst READ Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition

Table 43. Burst READ Timing Parameters—BCR[8] = 0

Symbol

70ns/80 MHz

85ns/66 MHz

Units

MinMax

tACLK

911

tCLK

12.5

tKHTL

911

tKOH

Table 42. Burst READ Timing Parameters—Burst Suspend (Continued)

Symbol

70ns/80 MHz

85ns/66 MHz

Units

MinMax

tOHZ

Don't Care

Legend:

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

A[22:0]

ADV#

CE#

LB#/UB#

WAIT

VIH

VIL

OE#

WE#

tCLK

VIH

VIL

CLK

(Note 2)

tKHTL

VOH

VOL

DQ[15:0]

tKOH

tACLK

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

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