DS2156 datasheet(4/240 Pages) MAXIM

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DS2155

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22.1

METHOD 1: HARDWARE SCHEME .........................................................................................................115

22.2

METHOD 2: INTERNAL REGISTER SCHEME BASED ON DOUBLE-FRAME ..............................................115

22.3

METHOD 3: INTERNAL REGISTER SCHEME BASED ON CRC4 MULTIFRAME........................................118

23.

HDLC CONTROLLERS........................................................................................................................128

23.1

BASIC OPERATION DETAILS..................................................................................................................128

23.2

HDLC CONFIGURATION........................................................................................................................128

23.2.1

FIFO Control....................................................................................................................................132

23.3

HDLC MAPPING....................................................................................................................................133

23.3.1

Receive..............................................................................................................................................133

23.3.2

Transmit............................................................................................................................................135

23.3.3

FIFO Information .............................................................................................................................140

23.3.4

Receive Packet-Bytes Available........................................................................................................140

23.3.5

HDLC FIFOs ....................................................................................................................................141

23.4

RECEIVE HDLC CODE EXAMPLE..........................................................................................................142

23.5

LEGACY FDL SUPPORT (T1 MODE)......................................................................................................142

23.5.1

Overview ...........................................................................................................................................142

23.5.2

Receive Section .................................................................................................................................142

23.5.3

Transmit Section ...............................................................................................................................144

23.6

D4/SLC-96 OPERATION ........................................................................................................................144

24.

LINE INTERFACE UNIT (LIU) ...........................................................................................................145

24.1

LIU OPERATION ....................................................................................................................................145

24.2

RECEIVER ..............................................................................................................................................145

24.2.1

Receive Level Indicator and Threshold Interrupt.............................................................................146

24.2.2

Receive G.703 Synchronization Signal (E1 Mode)...........................................................................146

24.2.3

Monitor Mode ...................................................................................................................................146

24.3

TRANSMITTER .......................................................................................................................................147

24.3.1

Transmit Short-Circuit Detector/Limiter..........................................................................................147

24.3.2

Transmit Open-Circuit Detector.......................................................................................................147

24.3.3

Transmit BPV Error Insertion ..........................................................................................................147

24.3.4

Transmit G.703 Synchronization Signal (E1 Mode).........................................................................147

24.4

MCLK PRESCALER ...............................................................................................................................148

24.5

JITTER ATTENUATOR.............................................................................................................................148

24.6

CMI (CODE MARK INVERSION) OPTION...............................................................................................148

24.7

LIU CONTROL REGISTERS ....................................................................................................................149

24.8

RECOMMENDED CIRCUITS.....................................................................................................................158

24.9

COMPONENT SPECIFICATIONS...............................................................................................................160

25.

PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION......................165

26.

BERT FUNCTION..................................................................................................................................172

26.1

STATUS ..................................................................................................................................................172

26.2

MAPPING ...............................................................................................................................................172

26.3

BERT REGISTER DESCRIPTIONS ...........................................................................................................174

26.4

BERT REPETITIVE PATTERN SET..........................................................................................................178

26.5

BERT BIT COUNTER .............................................................................................................................179

26.6

BERT ERROR COUNTER .......................................................................................................................180

27.

PAYLOAD ERROR-INSERTION FUNCTION (T1 MODE ONLY)................................................182

27.1

NUMBER-OF-ERRORS REGISTERS..........................................................................................................184

27.1.1

Number-of-Errors Left Register........................................................................................................185

28.

INTERLEAVED PCM BUS OPERATION (IBO)...............................................................................186

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