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CY7C006
CY7C016
9
Notes:
24. Data I/O pins enter high-impedance when OE is held LOW during write.
25. CE = HIGH for the duration of the above timing (both write and read cycle).
Switching Waveforms (continued)
tAW
tWC
tSCE
tSA
tPWE
tHD
tSD
tHZWE
tHA
HIGH IMPEDANCE
SEM OR CE
R/W
ADDRESS
DATA OUT
DATA IN
tLZWE
DATA VALID
C006-14
Write Cycle No. 2: R/W Three-State Data I/Os (Either Port)[20, 22, 24]
tSOP
SEM
R/W
OE
I/O 0
C006-15
VALID ADDRESS
VALID ADDRESS
tHD
DATAIN VALID
DATAOUT VALID
tOHA
A0–A2
tHA
tACE
tSOP
tSCE
tSD
tSA
tPWE
tSWRD
tDOE
WRITE CYCLE
READ CYCLE
Semaphore Read After Write Timing, Either Side[25]
tAW
tAA