CY7C006
CY7C016
13
Architecture
The CY7C006/016 consists of a an array of 16K words of 8/9
bits each of dual-port RAM cells, I/O and address lines, and
control signals (CE, OE, R/W). These control pins permit indepen-
dent access for reads or writes to any location in memory. To handle
simultaneous writes/reads to the same location, a BUSY pin is pro-
vided on each port. Two Interrupt (INT) pins can be utilized for
port-to-port communication. Two Semaphore (SEM) control pins are
used for allocating shared resources. With the M/S pin, the
CY7C006/016 can function as a Master (BUSY pins are outputs) or
as a slave (BUSY pins are inputs). The CY7C006/016 has an auto-
matic power-down feature controlled by CE. Each port is provided
with its own Output Enable control (OE), which allows data to be read
from the device.
Functional Description
Write Operation
Data must be set up for a duration of tSD before the rising edge
of R/W in order to guarantee a valid write. A write operation is con-
trolled by either the OE pin (see Write Cycle No.1 waveform) or the
R/W pin (see Write Cycle No. 2 waveform). Data can be written to the
device tHZOE after the OE is deasserted or tHZWE after the falling
edge of R/W. Required inputs for non-contention operations are sum-
marized in Table 1.
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must be met before the data is read on the output; oth-
erwise the data read is not deterministic. Data will be valid on
the port tDDD after the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE
and CE pins. Data will be available tACE after CE or tDOE after OE are
asserted. If the user of the CY7C006/016 wishes to access a sema-
phore flag, then the SEM pin must be asserted instead of the CE pin.
Interrupts
The interrupt flag (INT) permits communications between ports.
When the left port writes to location 3FFF(HEX), the right port’s inter-
rupt flag (INTR) is set. This flag is cleared when the right port reads
that same location. Setting the left port’s interrupt flag (INTL) is ac-
complished when the right port writes to location 3FFE(HEX). This
flag is cleared when the left port reads location 3FFE(HEX). The mes-
sage at 3FFE(HEX) and 3FFF(HEX) is user-defined. See Table 2 for
input requirements for INT. INTR and INTL are push-pull outputs and
do not require pull-up resistors to operate.
Busy
The CY7C006/016 provides on-chip arbitration to resolve si-
multaneous memory location access (contention). If both
ports’ CEs are asserted and an address match occurs within tPS of
each other the Busy logic will determine which port has access. If tPS
is violated, one port will definitely gain permission to the location, but
it is not guaranteed which one. BUSY will be asserted tBLA after an
address match or tBLC after CE is taken LOW. BUSYL and BUSYR
in master mode are push-pull outputs and do not require pull-up re-
sistors to operate.
Master/Slave
An M/S pin is provided in order to expand the word width by config-
uring the device as either a master or a slave. The BUSY output of
the master is connected to the BUSY input of the slave. This will allow
the device to interface to a master device with no external compo-
nents. Writing of slave devices must be delayed until after the BUSY
input has settled (tBLA). Otherwise, the slave chip may begin a write
cycle during a contention situation. When presented a HIGH input,
the M/S pin allows the device to be used as a master and therefore
the BUSY line is an output. BUSY can then be used to send the
arbitration outcome to a slave.
Semaphore Operation
The CY7C006/016 provides eight semaphore latches which
are separate from the dual-port memory locations. Sema-
phores are used to reserve resources that are shared between
the two ports.The state of the semaphore indicates that a re-
source is in use. For example, if the left port wants to request
a given resource, it sets a latch by writing a 0 to a semaphore
location. The left port then verifies its success in setting the
latch by reading it. After writing to the semaphore, SEM or OE
must be deasserted for tSOP before attempting to read the sema-
phore. The semaphore value will be available tSWRD + tDOE after the
rising edge of the semaphore write. If the left port was successful
(reads a 0), it assumes control over the shared resource, otherwise
(reads a 1) it assumes the right port has control and continues to poll
the semaphore.When the right side has relinquished control of the
semaphore (by writing a 1), the left side will succeed in gaining control
of the semaphore. If the left side no longer requires the semaphore,
a 1 is written to cancel its request.
Table 1. Non-Contending Read/Write
Inputs
Outputs
CE
R/W
OE
SEM
I/O0–7/8
Operation
H
X
X
H
High Z
Power-Down
H
H
L
L
Data Out
Read Data in
Semaphore
X
X
H
X
High Z
I/O Lines Disabled
H
X
L
Data In
Write to Semaphore
L
H
L
H
Data Out
Read
L
L
X
H
Data In
Write
L
X
X
L
Illegal Condition
Table 2. Interrupt Operation Example (assumes BUSYL=BUSYR=HIGH)
Left Port
Right Port
Function
R/W
CE
OE
A0L–13L
INT
R/W
CE
OE
A0R–13R
INT
Set Left INT
X
X
X
X
L
L
L
X
3FFE
X
Reset Left INT
X
L
L
3FFE
H
X
L
L
X
X
Set Right INT
L
L
X
3FFF
X
X
X
X
X
L
Reset Right INT
X
X
X
X
X
X
L
L
3FFF
H
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