CY7C006
CY7C016
14
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip enable for the semaphore latches (CE must
remain HIGH during SEM LOW). A0–2 represents the semaphore
address. OE and R/W are used in the same manner as a normal
memory access.When writing or reading a semaphore, the other ad-
dress pins have no effect.
When writing to the semaphore, only I/O0 is used. If a 0 is written
to the left port of an unused semaphore, a 1 will appear at the same
semaphore address on the right port. That semaphore can now only
be modified by the side showing 0 (the left port in this case). If the left
port now relinquishes control by writing a 1 to the semaphore, the
semaphore will be set to 1 for both sides. However, if the right port had
requested the semaphore (written a 0) while the left port had control,
the right port would immediately own the semaphore as soon as the
left port released it. Table 3 shows sample semaphore operations.
When reading a semaphore, all eight data lines output the
semaphore value. The read value is latched in an output reg-
ister to prevent the semaphore from changing state during a
write from the other port. If both ports attempt to access the
semaphore within tSPS of each other, the semaphore will definitely
be obtained by one side or the other, but there is no guarantee which
side will control the semaphore.
Initialization of the semaphore is not automatic and must be
reset during initialization program at power-up. All Sema-
phores on both sides should have a one written into them at
initialization from both sides to assure that they will be free
when needed.
Table 3. Semaphore Operation Example
Function
I/O0-7/8 Left
I/O0-7/8 Right
Status
No action
1
1
Semaphore free
Left port writes semaphore
0
1
Left port obtains semaphore
Right port writes 0 to semaphore
0
1
Right side is denied access
Left port writes 1 to semaphore
1
0
Right port is granted access to semaphore
Left port writes 0 to semaphore
1
0
No change. Left port is denied access
Right port writes 1 to semaphore
0
1
Left port obtains semaphore
Left port writes 1 to semaphore
1
1
No port accessing semaphore address
Right port writes 0 to semaphore
1
0
Right port obtains semaphore
Right port writes 1 to semaphore
1
1
No port accessing semaphore
Left port writes 0 to semaphore
0
1
Left port obtains semaphore
Left port writes 1 to semaphore
1
1
No port accessing semaphore
Ordering Information
16K x8 Dual-Port SRAM
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
15
CY7C006-15AC
A65
64-Lead Thin Quad Flat Package
Commercial
CY7C006-15JC
J81
68-Lead Plastic Leaded Chip Carrier
25
CY7C006-25AC
A65
64-Lead Thin Quad Flat Package
Commercial
CY7C006-25JC
J81
68-Lead Plastic Leaded Chip Carrier
CY7C006-25AI
A65
64-Lead Thin Quad Flat Package
Industrial
CY7C006-25JI
J81
68-Lead Plastic Leaded Chip Carrier
35
CY7C006-35AC
A65
64-Lead Thin Quad Flat Package
Commercial
CY7C006-35JC
J81
68-Lead Plastic Leaded Chip Carrier
CY7C006-35AI
A65
64-Lead Thin Quad Flat Package
Industrial
CY7C006-35JI
J81
68-Lead Plastic Leaded Chip Carrier
55
CY7C006-55AC
A65
64-Lead Thin Quad Flat Package
Commercial
CY7C006-55JC
J81
68-Lead Plastic Leaded Chip Carrier
CY7C006-55AI
A65
64-Lead Thin Quad Flat Package
Industrial
CY7C006-55JI
J81
68-Lead Plastic Leaded Chip Carrier
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