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CY7C006
CY7C016
3
Pin Definitions
Pin Configurations (continued)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
17
16
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
44
45
43
42
41
80-Pin TQFP
Top View
I/O 2L
I/O
3L
I/O 4L
I/O 5L
I/O
6L
I/O 7L
V CC
GND
I/O0R
I/O1R
2R
I/O 3R
I/O 4R
5R
GND
V CC
A5L
A4L
A3L
A2L
A1L
A0L
GND
BUSYL
M/S
A0R
A1R
A2R
A3R
A4R
INTL
I/O 6R
CY7C016
BUSYR
INTR
NC
NC
NC
C006-4
NC
NC
I/O
I/O
NC
Left Port
Right Port
Description
I/O0L–7L(8L)
I/O0R–7R(8R)
Data Bus Input/Output
A0L–13L
A0R–13R
Address Lines
CEL
CER
Chip Enable
OEL
OER
Output Enable
R/WL
R/WR
Read/Write Enable
SEML
SEMR
Semaphore Enable. When asserted LOW, allows access to eight sema-
phores. The three least significant bits of the address lines will determine
which semaphore to write or read. The I/O0 pin is used when writing to a
semaphore. Semaphores are requested by writing a 0 into the respective
location.
INTL
INTR
Interrupt Flag. INTL is set when right port writes location 3FFE and is
cleared when left port reads location 3FFE. INTR is set when left port writes
location 3FFF and is cleared when right port reads location 3FFF.
BUSYL
BUSYR
Busy Flag
M/S
Master or Slave Select
VCC
Power
GND
Ground
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