ADF4193 datasheet(6/28 Pages) AD

6 / 28 page

ADF4193

Rev. B | Page 6 of 28

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CMR

AOUT

SW3

AGND1

RFIN–

RFIN+

AVDD1

VP2

RSET

AGND2

DGND3

VP1

DATA

CLK

DVDD1

ADF4193

TOP VIEW

PIN 1

INDICATOR

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

CMR

Common-Mode Reference Voltage for the Differential Amplifier’s Output Voltage Swing. Internally biased to

three-fifths of VP3. Requires a 0.1 μF capacitor to ground.

AOUT

Differential Amplifier Output to Tune the External VCO.

SW3

Fast-Lock Switch 3. Closed while SW3 timeout counter is active.

AGND1

Analog Ground. This is the ground return pin for the differential amplifier and the RF section.

RFIN−

Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a small bypass

capacitor, typically 100 pF.

RFIN+

Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.

AVDD1

Power Supply Pin for the RF Section. Nominally 3 V. A 100 pF decoupling capacitor to the ground plane should be

placed as close as possible to this pin.

DVDD1

Power Supply Pin for the N Divider. Should be the same voltage as AVDD1. A 0.1 μF decoupling capacitor to ground

should be placed as close as possible to this pin.

DGND1

Ground Return Pin for DVDD1.

DVDD2

Power Supply Pin for the REFIN Buffer and R Divider. Nominally 3 V. A 0.1 μF decoupling capacitor to ground

should be placed as close as possible to this pin.

REFIN

Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of

100 kΩ (see Figure 15). This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled.

DGND2

Ground Return Pin for DVDD2 and DVDD3.

DVDD3

Power Supply Pin for the Serial Interface Logic. Nominally 3 V.

SDGND

Ground Return Pin for the Σ-Δ Modulator.

SDVDD

Power Supply Pin for the Digital Σ-Δ Modulator. Nominally 3 V. A 0.1 μF decoupling capacitor to the ground plane

should be placed as close as possible to this pin.

MUXOUT

Multiplexer Output. This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference

frequency to be accessed externally (see Figure 35).

CLK

Serial Clock Input. Data is clocked into the 24-bit shift register on the CLK rising edge. This input is a high

impedance CMOS input.

DATA

Serial Data Input. The serial data is loaded MSB first with the three LSBs as the control bits. This input is a high

impedance CMOS input.

Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register that is

selected by the three LSBs.

VP1

Power Supply Pin for the Phase Frequency Detector (PFD). Nominally 5 V, should be at the same voltage at VP2.

A 0.1 μF decoupling capacitor to ground should be placed as close as possible to this pin.

DGND3

Ground Return Pin for VP1.

AGND2

Ground Return Pin for VP2.

ADF4193 Datasheet(PDF) 6 Page - Analog Devices

ADF4193 Datasheet(HTML) 6 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL