ADF4193 datasheet(22/28 Pages) AD

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ADF4193

Rev. B | Page 22 of 28

PROGRAMMING

The ADF4193 can synthesize output frequencies with a channel

step or resolution that is a fraction of the input reference frequency.

For a given input reference frequency and a desired output

frequency step, the first choice to make is the PFD reference

frequency and the MOD. Once these are chosen, the desired

output frequency channels are set by programming the INT

and FRAC values.

WORKED EXAMPLE

In this example of a GSM900 RX system, it is required to

generate RF output frequencies with channel steps of 200 kHz.

A 104 MHz reference frequency input (REFIN) is available. The

R divider setting that set the PFD reference is shown in

Equation 1.

FPFD = REFIN × [(1 + D)/(R × (1 + T))]

(1)

where:

REFIN is the input reference frequency.

D is the doubler enable bit (0 or 1).

R is the 4-bit R counter code (0…15).

T is the REF/2 bit (0 or 1).

The maximum PFD reference frequency of 26 MHz is chosen

and the following settings are programmed to give an R divider

value of 4:

Doubler enable = 0

R = 2

REF/2 = 1

Next, the modulus is chosen to allow fractional steps of 200 kHz.

MOD = 26 MHz/200 kHz = 130

(2)

Once the channel step is defined, the following equation shows

how output frequency channels are programmed:

RFOUT = [INT + (FRAC/MOD] × [FPFD]

(3)

where:

RFOUT is the desired RF output frequency.

INT is the integer part of the division.

FRAC is the numerator part of the fractional division.

MOD is the modulus or denominator part of the fractional

division.

For example, the frequency channel at 962.4 MHz is synthesized

by programming the following values:

INT = 37

FRAC = 2

SPUR MECHANISMS

The Fractional Spurs, Integer Boundary Spurs, and Reference

Spurs sections describe the three different spur mechanisms

that arise with a fractional-N synthesizer and how the ADF4193

can be programmed to minimize them.

Fractional Spurs

The fractional interpolator in the ADF4193 is a third-order, Σ-Δ

modulator (SDM) with a modulus (MOD) that is programmable to

any integer value from 13 to 4095. If dither is enabled, then the

minimum allowed value of MOD is 50. The SDM is clocked at

the PFD reference rate (fPFD) that allows PLL output frequencies

to be synthesized at a channel step resolution of fPFD/MOD.

With dither turned off, the quantization noise from the Σ-Δ

modulator appears as fractional spurs. The interval between

spurs is fPFD/L, where L is the repeat length of the code sequence

in the digital Σ-Δ modulator. For the third-order modulator

used in the ADF4193, the repeat length depends on the value of

MOD, as shown in Table 7.

Table 7. Fractional Spurs with Dither Off

Condition (Dither Off)

Repeat Length

Spur Interval

If MOD is divisible by 2,

but not 3

2 × MOD

Channel step/2

If MOD is divisible by 3,

but not 2

3 × MOD

Channel step/3

If MOD is divisible by 6

6 × MOD

Channel step/6

Otherwise

MOD

Channel step

With dither enabled, the repeat length is extended to 221 cycles,

regardless of the value of MOD, which makes the quantization

error spectrum look like broadband noise. This can degrade the

in-band phase noise at the PLL output by as much as 10 dB.

Therefore, for the lowest noise, dither off is a better choice,

particularly when the final loop BW is low enough to attenuate

even the lowest frequency fractional spur. The wide loop

bandwidth range available with the ADF4193 makes this

possible in most applications.

Integer Boundary Spurs

Another mechanism for fractional spur creation involves

interactions between the RF VCO frequency and the reference

frequency. When these frequencies are not integer related, spur

sidebands appear on the VCO output spectrum at an offset

frequency that corresponds to the beat note or difference

frequency between an integer multiple of the reference and the

VCO frequency.

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