ADF4193 datasheet(18/28 Pages) AD

Part #	ADF4193

Description	Low Phase Noise, Fast Settling PLL Frequency Synthesizer

PDF	28 Pages

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Manufacturer	AD [Analog Devices]

Direct Link	http://www.analog.com

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18 / 28 page

ADF4193

Rev. B | Page 18 of 28

FUNCTION REGISTER (R3)

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

C3 (0)

DB1

C2 (1)

DB0

C1 (1)

RESERVED

CONTROL

BITS

NEGATIVE

POSITIVE

PFD POLARITY

CPO/CPO GND

NORMAL

CPO GND

Figure 32. Function Register (R3)

R3, the function register (C3, C2, C1 set to 0, 1, 1, respectively),

only needs to be programmed during the initialization sequence

(see Table 8).

CPO GND

When the CPO GND bit is low, the charge pump outputs are

internally pulled to ground. This is invoked during the

initialization sequence to discharge the loop filter capacitors.

For normal operation, this bit should be high.

PFD Polarity

This bit should be set to 1 for positive polarity and set to 0 for

negative polarity.

Reserved Bits

The Bit DB15 to Bit DB6 are reserved bits and should be

programmed to hex code 001, and Reserved Bit DB4 should be

set to 1.

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