ADF4251 datasheet(25/28 Pages) AD

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REV. 0

ADF4251

–25–

IF Side Not In Use

If the IF side is not being used, the following pinout is recom-

mended for the IF side:

Pin No.

Mnemonic

Description

AGND2

Short to all other ground pins.

IFINBLeave open circuit. (This is biased

up to VDD/2 internally.)

IFINALeave open circuit. (This is biased

up to VDD/2 internally.)

CP_IF

Leave open circuit. (This is internally

three-stated until power-up.)

VP2

Short to VP1. (VP1 is the RF CP

supply.)

VDD2

Short to VDD1 (VDD1 is the RF VDD

supply.)

INTERFACING

The ADF4251 has a simple SPI compatible serial interface for

writing to the device. SCLK, SDATA, and LE control the data

transfer. When LE (Latch Enable) goes high, the 24 bits that have

been clocked into the input register on each rising edge of SCLK

will be transferred to the appropriate latch. See Figure 1 for the

Timing Diagram and Table I for the Control Bit Truth Table.

The maximum allowable serial clock rate is 20 MHz. This means

that the maximum update rate possible for the device is 833 kHz

or one update every 1.2 µs. This is certainly more than adequate

for systems that will have typical lock times in hundreds of

microseconds.

ADuC812

ADF4251

SCLK

SDATA

MUXOUT

(LOCK DETECT)

SCLOCK

MOSI

I/O PORTS

Figure 8. ADuC812 to ADF4251 Interface

ADuC812 Interface

Figure 8 shows the interface between the ADF4251 and the

ADuC812 microconverter. Since the ADuC812 is based on

an 8051 core, this interface can be used with any 8051-based

microcontroller. The microconverter is set up for SPI Master

mode with CPHA = 0. To initiate the operation, the I/O port

driving LE is brought low. Each latch of the ADF4251 needs

(at most) a 24-bit word. This is accomplished by writing three

8-bit bytes from the microconverter to the device. When the third

byte has been written, the LE input should be brought high to

complete the transfer.

I/O port lines on the ADuC812 are also used to control power-

down (CE input) and to detect lock (MUXOUT configured as

lock detect and polled by the port input).

When operating in the mode described, the maximum SCLOCK

rate of the ADuC812 is 4 MHz. This means that the maximum

rate at which the output frequency can be changed will be 166 kHz.

RF VCO

VCC

RF LOOP

FILTER

GND

ADF4251

RFOUT

100pF

DECOUPLING CAPACITORS AND INTERFACE SIGNALS

HAVE BEEN OMITTED FROM THE DIAGRAM IN THE

INTERESTS OF GREATER CLARITY.

100pF

RFINA

RFINB

REFIN

VDD

VDD DVDD VP

RF CP

2.7k

POWER-DOWN CONTROL

ADG702

SVDD

GND

RSET

IFOUT

100pF

IF VCO

VCC

GND

IF LOOP

FILTER

100pF

IFINA

IFINB

IF CP

Figure 9. Power-Down Circuit

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