TSI721 datasheet(29/67 Pages) RENESAS

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Tsi721 Datasheet

April 4, 2016

Integrated Device Technology

3.4

Power Supply Sequencing

This section contains power-up and power-down supply sequencing for the Tsi721.

3.4.1

Power-Up Sequencing

The Tsi721 must have its supplies powered up as follows:

1. VDD and AVDD10 (1.0V) must be powered up together.

To achieve this requirement AVDD10 can be supplied from the same regulator as VDD, but must be isolated on the board

through a ferrite bead.

2. VDDIO, AVDD25, AVTT, and the 1.0V supplies (VDD and AVDD10) can be powered up in any order.

3. The voltages on any input or I/O pin cannot exceed its corresponding supply voltage during power supply ramp up.

4. The power supply ramp rates must be kept between 10 V/s and 0.5x10E6 V/s to minimize power current spikes during power

up. This leads to the ramp times specified in the following table.

3.4.2

Power-Down Sequencing

The Tsi721 must have its supplies powered down as follows:

1. VDD and AVDD10 (1.0V) must be powered down together. To achieve this requirement AVDD10 can be supplied from the

same regulator as VDD, but must be isolated on the board through a ferrite bead.

2. VDDIO, AVDD25, AVTT, and the 1.0V supplies (VDD and AVDD10) can be powered down in any order.

-40

Max.

1.05

829

1.05

192

2.75

159

1.70

350

3.47

2.17

Typ.

1.00

765

1.00

175

2.50

149

1.50

335

3.30

1.87

Min.

0.95

707

0.95

159

2.25

141

1.40

320

3.14

1.64

Table 14: Power Supply Sequencing Ramp Times

V/s

5.00E+05

3.3

330000 us

6.6 us

2.5

250000 us

5 us

1.5

150000 us

3 us

100000 us

2 us

Table 13: Power Consumption (Continued)

Junction

Temp

(0C)

Voltage

VDD

AVDD10

AVDD25

AVTT

VDDIO

Total

Power (W)

Voltage

(V)

Current

[mA]

Voltage

(V)

Current

[mA]

Voltage

(V)

Current

[mA]

Voltage

(V)

Current

[mA]

Voltage

(V)

Current

[mA]

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