TSI721 datasheet(57/67 Pages) RENESAS

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Tsi721 Datasheet

April 4, 2016

Integrated Device Technology

3.7.5

Reference Clocks – PCCLKP/N and REFCLKP/N

Table 32 lists the PCCLKP/N and REFCLKP/N clock electrical characteristics of the Tsi721.

PCCLKP/N and REFCLKP/N require a terminated, DC biased, differential clock source. This type of reference clock is usually

used in PCIe systems but not in S-RIO systems. Different clock technologies can be used with the Tsi721 provided that proper

termination is used.

The following diagrams provide examples of commonly used clock technologies connected to PCCPLKP/N and REFCLKP/N.

The clock source that drives the PCCLK inputs must meet all requirements for the common clock

architecture defined for the reference clock in the PCI Express Base Specification (Rev. 2.1).

Table 32: PCCLKP/N and REFCLKP/NClock Electrical Characteristics

Symbol

Parameter

Minimum

Typical

Maximum

Unit

VIN_DIFF

Differential input voltage (single-ended peak

to peak)

0.3

1.0

VDC

Input level

2.5

VCMa

a. Common-mode voltage must be supplied by the clock source circuit.

Common-mode input level

0.15

2.0

FREFCLK

REFCLK clock frequency

100

156.25

MHz

SREFCLK

REFCLK stability

-100

+100

ppm

TJREFCLK

REFCLK total phase jitter (1 MHz–20 MHz)

ps (rms)

FPCCLK

PCCLK clock frequency

100

156.25

MHz

SPCCLK

PCCLK average frequency accuracy

-300

300

ppm

CCJPCCLK

PCCLK cycle-to-cycle jitter

150

FDUTY

Clock duty cycle

TER-RISE

Rising edge rate

0.6

V/ns

TER-FALL

Falling edge rate

0.6

V/ns

Zinb

b. Clock termination must be implemented on the circuit board.

Clock input impedance

High

Ohm

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