TSI721 datasheet(11/67 Pages) RENESAS

11 / 67 page

Tsi721 Datasheet

April 4, 2016

Integrated Device Technology

• Round-robin scheduling among DMA channels

• DMA descriptors for all channels reside on PCIe side

• Scatter-and-gather with descriptor list

• Supports DMA strides

• Supports up to 64 MB data for a single descriptor

• Supports both read and write descriptors per DMA channel

• Dynamic descriptor chaining

• Flexible addressing modes

— Linear addressing

— Constant addressing

• Descriptor prefetch

• 32 outstanding PCIe requests to root complex

• 64 outstanding S-RIO NREAD/maintenance read requests to S-RIO network

• 64 outstanding S-RIO NWRITE_R/maintenance write requests to S-RIO network

• Supports the following S-RIO transactions:

— NREAD

—NWRITE

—SWRITE

—NWRITE_R

— Maintenance read

— Maintenance write

1.2.6

Miscellaneous Features

•I2C interface supports the following:

— As a slave, being read/written by an external master during normal operations

— As a master, reading external EEPROM during boot load

— As a master, reading/writing other external devices during normal operations

• JTAG 1149.1, 1149.6 (AC JTAG)

• 16 GPIO pins

TSI721 Datasheet(PDF) 11 Page - Renesas Technology Corp