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ST7789V2 Datasheet(PDF) 126 Page - Sitronix Technology Co., Ltd.

Part # ST7789V2
Description  Single chip TFT-LCD Controller/Driver with On-chip Frame Memory (FM)
PDF  319 Pages
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Manufacturer  SITRONIX [Sitronix Technology Co., Ltd.]
Direct Link  http://www.sitronix.com.tw
Logo SITRONIX - Sitronix Technology Co., Ltd.

ST7789V2 Datasheet(HTML) 126 Page - Sitronix Technology Co., Ltd.

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ST7789V2
Version 1.0
Page 126 of 319
2016/11
Sitronix Confidential
The information contained herein is the exclusive property of Sitronix and shall not be distributed, reproduced, or
disclosed in whole or in part without prior written permission of Sitronix.
8.12 Address Control
The address counter sets the addresses of the display data RAM for writing and reading.
Data is written pixel-wise into the RAM matrix of DRIVER. The data for one pixel or two pixels is collected
(RGB 6-6-6-bit), according to the data formats. As soon as this pixel-data information is complete the “Write
access” is activated on the RAM. The locations of RAM are addressed by the address pointers. The address
ranges are X=0 to X=239 (Efh) and Y=0 to Y=319 (13Fh). Addresses outside these ranges are not allowed.
Before writing to the RAM, a window must be defined that will be written. The window is programmable via
the command registers XS, YS designating the start address and XE, YE designating the end address.
For example the whole display contents will be written, the window is defined by the following values:
XS=0 (0h) YS=0 (0h) and XE=239 (Efh), YE=319 (13Fh).
In vertical addressing mode (MV=1), the Y-address increments after each byte, after the last Y-address
(Y=YE), Y wraps around to YS and X increments to address the next column. In horizontal addressing mode
(V=0), the X-address increments after each byte, after the last X-address (X=XE), X wraps around to XS and
Y increments to address the next row. After the every last address (X=XE and Y=YE) the address pointers
wrap around to address (X=XS and Y=YS).
For flexibility in handling a wide variety of display architectures, the commands “CASET, RASET and
MADCTL”, define flags MX and MY, which allows mirroring of the X-address and Y-address. All combinations
of flags are allowed. Section 8.12 show the available combinations of writing to the display RAM. When MX,
MY and MV will be changed the data bust be rewritten to the display RAM.
For each image condition, the controls for the column and row counters apply as below
Condition
Column Counter
Row Counter
When RAMWR/RAMRD command is accepted
Return to
“Start Column (XS)”
Return to
“Start Row (YS)”
Complete Pixel Read / Write action
Increment by 1
No change
The Column counter value is larger than “End Column (XE)”
Return to
“Start Column (XS)”
Increment by 1
The Column counter value is larger than “End Column (XE)”
and the Row counter value is larger than “End Row (YE)”
Return to
“Start Column (XS)”
Return to
“Start Row (YS)”



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