MC68340 datasheet(320/441 Pages) FREESCALE

320 / 441 page

MOTOROLA

MC68340 USER’S MANUAL

7- 25

OE—Overrun Error

1 = One or more characters in the received data stream have been lost. This bit is

set upon receipt of a new character when the FIFO is full and a character is

already in the shift register waiting for an empty FIFO position. When this occurs,

the character in the receiver shift register and its break detect, framing error

status, and parity error, if any, are lost. This bit is cleared by the reset error status

command in the CR.

0 = No overrun has occurred.

TxEMP—Transmitter Empty

1 = The channel transmitter has underrun (both the transmitter holding register and

transmitter shift registers are empty). This bit is set after transmission of the last

stop bit of a character if there are no characters in the transmitter holding register

awaiting transmission.

0 = The transmitter buffer is not empty. The transmitter holding register is loaded by

the CPU32, or the transmitter is disabled. The transmitter is enabled/disabled by

programming the TCx bits in the CR.

TxRDY—Transmitter Ready

This bit is duplicated in the ISR; bit 0 for channel A and bit 4 for channel B.

1 = The transmitter holding register is empty and ready to be loaded with a character.

This bit is set when the character is transferred to the transmitter shift register.

This bit is also set when the transmitter is first enabled. Characters loaded into

the transmitter holding register while the transmitter is disabled are not

transmitted and are lost.

0 = The transmitter holding register was loaded by the CPU32, or the transmitter is

disabled.

FFULL—FIFO Full

1 = A character was transferred from the receiver shift register to the receiver FIFO

and the transfer caused the FIFO to become full (all three FIFO holding register

positions are occupied).

0 = The CPU32 has read the receiver buffer and one or more FIFO positions are

available. Note that if there is a character in the receiver shift register because

the FIFO is full, this character will be moved into the FIFO when a position is

available, and the FIFO will remain full.

RxRDY—Receiver Ready

1 = A character has been received and is waiting in the FIFO to be read by the

CPU32. This bit is set when a character is transferred from the receiver shift

0 = The CPU32 has read the receiver buffer, and no characters remain in the FIFO

after this read.

Freescale Semiconductor, Inc.

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