MC68340 datasheet(362/441 Pages) FREESCALE

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8- 18

MC68340 USER’S MANUAL

MOTOROLA

TIMER 1

TIMER 2

$600

$640

MODULE CONFIGURATION REGISTER (MCR)

$602

$642

RESERVED

$604

$644

INTERRUPT REGISTER (IR)

$606

$646

S/U

CONTROL REGISTER (CR)

$608

$648

S/U

STATUS/PRESCALER REGISTER (SR)

$60A

$64A

S/U

COUNTER REGISTER (CNTR)

$60C

$64C

S/U

PRELOAD 1 REGISTER (PREL1)

$60E

$64E

S/U

PRELOAD 2 REGISTER (PREL2)

$610

$650

S/U

COMPARE REGISTER (COM)

$612-$63F

$652-$67F

S/U

RESERVED

Figure 8-11. Timer Module Programming Model

In the registers discussed in the following paragraphs, the numbers in the upper right-

hand corner indicate the offset of the register from the base address specified by the

module base address register (MBAR) in the SIM40. The first number is the offset for

timer 1; the second number is the offset for timer 2. The numbers on the top line of the

the bit. The value of these bits after a hardware reset is shown below the register. The

access privilege is shown in the lower right-hand corner.

NOTE

A CPU32 RESET instruction will not affect the MCR, but will

reset all other registers in the timer modules as though a

hardware reset occurred.

The term 'timer' is used to reference either timer 1 or timer 2, since the two are functionally

equivalent.

8.4.1 Module Configuration Register (MCR)

The MCR controls the timer module configuration. This register can be either read or

written when the module is enabled and is in the supervisor state. The MCR is not

affected by a CPU32 RESET instruction.

MCR

$600, $640

9876543210

STP

FRZ1

FRZ0

00000

SUPV

IARB3

IARB2

IARB1

IARB0

RESET:

0000000010000000

Supervisor Only

Freescale Semiconductor, Inc.

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