DP83848M datasheet(21/72 Pages) NSC

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The Start code is indicated by a <01> pattern. This assures

the MDIO line transitions from the default idle line state.

Turnaround is defined as an idle bit time inserted between

the Register Address field and the Data field. To avoid con-

tention during a read transaction, no device shall actively

drive the MDIO signal during the first bit of Turnaround.

The addressed DP83848M/J drives the MDIO with a zero

for the second bit of turnaround and follows this with the

required data. Figure 4 shows the timing relationship

between MDC and the MDIO as driven/received by the Sta-

tion (STA) and the DP83848M/J (PHY) for a typical register

read access.

For write transactions, the station management entity

writes data to the addressed DP83848M/J thus eliminating

the requirement for MDIO Turnaround. The Turnaround

time is filled by the management entity by inserting <10>.

Figure 5 shows the timing relationship for a typical MII reg-

ister write access.

3.2.3 Serial Management Preamble Suppression

The DP83848M/J supports a Preamble Suppression mode

as indicated by a one in bit 6 of the Basic Mode Status

entity (i.e. MAC or other management controller) deter-

mines that all PHYs in the system support Preamble Sup-

pression by returning a one in this bit, then the station

management entity need not generate preamble for each

management transaction.

The DP83848M/J requires a single initialization sequence

of 32 bits of preamble following hardware/software reset.

This requirement is generally met by the mandatory pull-up

resistor on MDIO in conjunction with a continuous MDC, or

the management access made to determine whether Pre-

amble Suppression is supported.

While the DP83848M/J requires an initial preamble

sequence of 32 bits for management initialization, it does

not require a full 32-bit sequence between each subse-

quent transaction. A minimum of one idle bit between man-

agement transactions is required as specified in the IEEE

802.3u specification.

Table 6. Typical MDIO Frame Format

MII Management

Serial Protocol

Read Operation

Write Operation

Figure 4. Typical MDC/MDIO Read Operation

Figure 5. Typical MDC/MDIO Write Operation

MDC

MDIO

00 0

110 0 00 000

(STA)

Idle

Start

Opcode

(Read)

PHY Address

(PHYAD = 0Ch)

(00h = BMCR)

MDIO

(PHY)

0 0 0 1 1 0 0 0 1 0 0 0000 0 0 Z

Idle

MDC

MDIO

11 0 0 0 0 000

(STA)

Idle

Start

Opcode

(Write)

PHY Address

(PHYAD = 0Ch)

(00h = BMCR)

0 0 0

0 00

0 0 0 0 0 000 Z

Idle

10 0

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