DP83848M datasheet(11/72 Pages) NSC

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1.3 CLOCK INTERFACE

1.4 LED INTERFACE

See Table 4 for LED Mode Selection.

1.5 RESET

COL

S, O, PU

MII COLLISION DETECT: Asserted high to indicate detection of

a collision condition (simultaneous transmit and receive activity)

in 10 Mb/s and 100 Mb/s Half Duplex Modes.

While in 10BASE-T Half Duplex mode with heartbeat enabled this

pin is also asserted for a duration of approximately 1

µs at the end

of transmission to indicate heartbeat (SQE test).

In Full Duplex Mode, for 10 Mb/s or 100 Mb/s operation, this sig-

nal is always logic 0. There is no heartbeat function during 10

Mb/s full duplex operation.

Signal Name

Type

Pin #

Description

CRYSTAL/OSCILLATOR INPUT: This pin is the primary clock

reference input for the DP83848M/J and must be connected to a

25 MHz 0.005% (+50 ppm) clock source. The DP83848M/J sup-

ports either an external crystal resonator connected across pins

X1 and X2, or an external CMOS-level oscillator source connect-

ed to pin X1 only.

CRYSTAL OUTPUT: This pin is the primary clock reference out-

put to connect to an external 25 MHz crystal resonator device.

This pin must be left unconnected if an external CMOS oscillator

clock source is used.

25MHz_OUT

25 MHz CLOCK OUTPUT:

This pin provides a 25 MHz clock output to the system.

This allows other devices to use the reference clock from the

DP83848M without requiring additional clock sources.

Note: This pin is not available in DP83848J.

Signal Name

Type

Pin #

Description

Signal Name

Type

Pin #

Description

LED_LINK

S, O, PU

LINK LED: In Mode 1, this pin indicates the status of the LINK.

The LED will be ON when Link is good.

LINK/ACT LED: In Mode 2, this pin indicates transmit and receive

activity in addition to the status of the Link. The LED will be ON

when Link is good. It will blink when the transmitter or receiver is

active.

LED_SPEED

S, O, PU

SPEED LED: This LED is ON when DP83848J is in 100Mb/s and

OFF when DP83848J is in 10Mb/s. Functionality of this LED is in-

dependent of the mode selected.

Note: This pin is not available in DP83848M.

Signal Name

Type

Pin #

Description

RESET_N

I, PU

RESET: Active Low input that initializes or re-initializes the

DP83848M/J. Asserting this pin low for at least 1

µs will force a

reset process to occur. All internal registers will re-initialize to their

default states as specified for each bit in the Register Block sec-

tion. All strap options are re-initialized as well.

DP83848M Datasheet(PDF) 11 Page - National Semiconductor (TI)

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