AD5360/AD5361

Preliminary Technical Data

Rev. P

rF | Page 12 of 25

FUNCTIONAL DESCRIPTION

DAC ARCHITECTURE—GENERAL

The AD5360/AD5361 contains 16 DAC channels and 16 output

amplifiers in a single package. The architecture of a single DAC

channel consists of a 16-bit resistor-string DAC in the case of

the AD5360 and a 14-bit DAC in the case of the AD5361,

followed by an output buffer amplifier. The resistor-string

section is simply a string of resistors, each of value R, from

VREF to AGND. This type of architecture guarantees DAC

monotonicity. The 16(14)-bit binary digital code loaded to the

DAC register determines at which node on the string the

voltage is tapped off before being fed into the output amplifier.

The output amplifier multiplies the DAC out voltage by 4. The

output span is 12 V with a 3 V reference and 20 V with a 5 V

reference.

CHANNEL GROUPS

The 16 DAC channels of the AD5360/AD5361 are arranged into

two groups of 8 channels. The eight DACs of Group 0 derive

their reference voltage from VREF0, and those of Group 1 from

VREF1.

Table 6. AD5360(AD5361) Registers

Register Name

Word Length (Bits)

Description

X1A (group)(channel)

16(14)

Input data register A, one for each DAC channel.

X1B (group) (channel)

16(14)

Input data register B, one for each DAC channel.

M (group) (channel)

16(14)

Gain trim registers, one for each DAC channel.

C (group) (channel)

16(14)

Offset trim registers, one for each DAC channel.

X2A (group)(channel)

16(14)

Output data register A, one for each DAC channel. These registers store the final,

calibrated DAC data after gain and offset trimming. They are not readable, nor directly

writable.

X2B (group) (channel)

16(14)

Output data register B, one for each DAC channel. These registers store the final,

calibrated DAC data after gain and offset trimming. They are not readable, nor directly

writable.

DAC (group) (channel)

Data registers from which the DACs take their final input data. The DAC registers are

updated from the X2A or X2B registers. They are not readable, nor directly writable.

OFS0

14

Offset DAC 0 data register, sets offset for Group 0.

OFS1

14

Offset DAC 1 data register, sets offset for Group 1.

Control

8

Bit 4 = Overtemperature indicator. 1 = chip temperature > 130 °C.

Bit 3 = PEC error flag. 1 = PEC error. Cleared on reading control register.

Bit 2 = A/B. 0 = global selection of X1A input data registers. 1 = X1B registers.

Bit 1 = Enable Temp Shutdown. 0 = disable temp shutdown. 1 = enable.

Bit 0 = Soft Power Down. 0 = soft power up. 1 = soft power down.

Monitor

6

Bit 5 = Monitor enable. 0 = off. 1 = on.

Bit 4 = 0, DAC selected by bits 3 to 0.

Bits 3 – 0 = DAC channel 0000 = 0 to 1111 = 15.

Bit 4 = 1, MON_IN pin selected by bit 0.

Bit 0 = MON_IN select. 0 = MON_IN0. 1 = MON_IN1.

GPIO

2

Bit 1 = GPIO configuration. 0 = input. 1 = output.

Bit 0 = GPIO data. Stores state of GPIO pin when input. Drives GPIO pin when

output.