Preliminary Technical Data

AD1935/AD1936/AD1937/AD1938/AD1939

Rev. Pr

I | Page 23 of 30

REGISTER DEFINITIONS

Register format

Global Address

R/W

Register Address

Data

Bit

23:17

16

15:8

7:0

Table 16

Note 2: Global address for the AD193X series is 0x04, shifted left 1 bit due to the R/W bit.

Note 4: All registers are reset to 0, except for the DAC volume registers which are set to full volume.

Register addresses and functions

Address

Function

0

PLL and Clock Control 0

1

PLL and Clock Control 1

2

DAC Control 0

3

DAC Control 1

4

DAC Control 2

5

DAC Individual Channel Mutes

6

DAC 1L Vol Control

7

DAC 1R Vol Control

8

DAC 2L Vol Control

9

DAC 2R Vol Control

10

DAC 3L Vol Control

11

DAC 3R Vol Control

12

DAC 4L Vol Control

13

DAC 4R Vol Control

14

ADC Control 0

15

ADC Control 1

16

ADC Control 2

Table 17