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EVAL-AD1938EB Datasheet(PDF) 25 Page - Analog Devices |
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EVAL-AD1938EB Datasheet(HTML) 25 Page - Analog Devices |
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25 / 30 page ![]() Preliminary Technical Data AD1935/AD1936/AD1937/AD1938/AD1939 Rev. Pr I | Page 25 of 30 DAC CONTROL REGISTERS DAC control 0 Bit Value Function Description 0 0 1 Normal Power down Power Down 2:1 00 01 10 11 32/44.1/48 kHz 64/88.2/96 kHz 128/176.4/192 kHz Reserved Sample Rate 5:3 000 001 010 011 100 101 110 111 1 0 8 12 16 Reserved Reserved Reserved SDATA Delay (BCLK periods) 7:6 00 01 10 11 Stereo (Normal) TDM (Daisy Chain) DAC Aux mode (ADC, DAC TDM coupled) Dual-line TDM Serial Format Table 20 DAC control 1 Bit Value Function Description 0 0 1 Latch in mid cycle (normal) Latch in at end of cycle (pipeline) BCLK Active Edge (TDM In) 2:1 00 01 10 11 64 (2 channels) 128 (4 channels) 256 (8 channels) 512 (16 channels) BCLKs Per Frame 3 0 1 Left low Left high LRCLK Polarity 4 0 1 Slave Master LRCLK Master/Slave 5 0 1 Slave Master BCLK Master/Slave 6 0 1 DBCLK pin Internally generated BCLK Source 7 0 1 Normal Inverted BCLK Polarity Table 21 |
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