AD5680 datasheet(13/20 Pages) AD

13 / 20 page

AD5680

Rev. 0 | Page 13 of 20

MICROPROCESSOR INTERFACING

AD5680 to Blackfin® ADSP-BF53x Interface

Figure 27 shows a serial interface between the AD5680 and

the Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x

processor family incorporates two dual-channel synchronous

serial ports, SPORT1 and SPORT0, for serial and multiprocessor

communications. Using SPORT0 to connect to the AD5680, the

setup for the interface is as follows. DT0PRI drives the DIN pin

of the AD5680, while TSCLK0 drives the SCLK of the part. The

SYNC is driven from TFS0.

AD5680*

*ADDITIONAL PINS OMITTED FOR CLARITY

TFS0

DTOPRI

TSCLK0

SYNC

DIN

SCLK

ADSP-BF53x*

Figure 27. AD5680 to Blackfin ADSP-BF53x Interface

AD5680 to 68HC11/68L11 Interface

Figure 28 shows a serial interface between the AD5680 and the

68HC11/68L11 microcontroller. SCK of the 68HC11/68L11

drives the SCLK of the AD5680, while the MOSI output drives

the serial data line of the DAC.

The SYNC signal is derived from a port line (PC7). The setup

conditions for correct operation of this interface are as follows.

The 68HC11/68L11 is configured with its CPOL bit as 0 and its

CPHA bit as 1. When data is being transmitted to the DAC, the

SYNC line is taken low (PC7). When the 68HC11/68L11 is

configured this way, data appearing on the MOSI output is valid

on the falling edge of SCK. Serial data from the 68HC11/68L11

is transmitted in 8-bit bytes with only eight falling clock edges

occurring in the transmit cycle. Data is transmitted MSB first. To

load data to the AD5680, PC7 is left low after the first eight bits

are transferred, and a second serial write operation is performed

to the DAC; PC7 is taken high at the end of this procedure.

AD5680*

*ADDITIONAL PINS OMITTED FOR CLARITY

PC7

SCK

MOSI

SYNC

SCLK

DIN

68HC11/68L11*

Figure 28. AD5680 to 68HC11/68L11 Interface

AD5680 to 80C51/80L51 Interface

Figure 29 shows a serial interface between the AD5680 and the

80C51/80L51 microcontroller. The setup for the interface is as

follows. TxD of the 80C51/80L51 drives SCLK of the AD5680,

while RxD drives the serial data line of the part. The SYNC

signal is again derived from a bit-programmable pin on the port.

In this case, port line P3.3 is used. When data is to be transmitted

to the AD5680, P3.3 is taken low. The 80C51/80L51 transmits

data in 8-bit bytes only; thus only eight falling clock edges occur

in the transmit cycle. To load data to the DAC, P3.3 is left low

after the first eight bits are transmitted, and a second write cycle

is initiated to transmit the second byte of data. P3.3 is taken

high following the completion of this cycle. The 80C51/80L51

outputs the serial data in a format that has the LSB first. The

AD5680 must receive data with the MSB first. The 80C51/80L51

transmit routine should take this into account.

80C51/80L51*

AD5680*

*ADDITIONAL PINS OMITTED FOR CLARITY

P3.3

TxD

RxD

SYNC

SCLK

DIN

Figure 29. AD5680 to 80C51/80L51 Interface

AD5680 to MICROWIRE Interface

Figure 30 shows an interface between the AD5680 and any

MICROWIRE-compatible device. Serial data is shifted out on

the falling edge of the serial clock and is clocked into the AD5680

on the rising edge of the SK.

MICROWIRE*

AD5680*

*ADDITIONAL PINS OMITTED FOR CLARITY

SYNC

SCLK

DIN

Figure 30. AD5680 to MICROWIRE Interface

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