AD71028 datasheet(12/20 Pages) AD

12 / 20 page

AD71028

Rev. 0 | Page 12 of 20

SPI PORT

CLATCH

CDATA

CCLK

BYTE 0

BYTE 1

BYTE 4

Figure 5. Sample of SPI Write Format (Single-Write Mode)

CLATCH

CCLK

CDATA

COUT

DATA

XXX

BYTE 0

BYTE 1

HI-Z

Figure 6. Sample of SPI Read Format (Single-Read Mode)

OVERVIEW

The AD71028 can be controlled using the SPI port. In general,

there are three parameters per processor that can be controlled:

the encoder output level, the Phat Stereo image enhancement

algorithm, and the dialog enhancement algorithm. It is also

possible to write new data into the parameter RAM to alter the

filter coefficients used in the BTSC encoding process. This is a

fairly complex topic unnecessary for normal operation of the

chip, and the details are not included in this data sheet. Please

contact ADI if modifications to the BTSC filters are required.

The SPI port uses a 4-wire interface consisting of CLATCH,

CCLK, CDATA, and COUT signals. The CLATCH signal goes

low at the beginning of a transaction and high at the end of a

transaction. The CCLK signal latches the serial input data on a

low-to-high transition. The CDATA signal carries the serial

input data, and the COUT signal is the serial output data. The

COUT signal remains three-stated until a READ operation is

requested. This allows other SPI compatible peripherals to share

the same readback line. All SPI transactions follow the same

basic format, shown in Figure 5. Figure 6 shows the read format.

The Wb/R bit is low for a write and high for a read operation.

The 10-bit address word is decoded into either a location in the

parameter RAM or one of the SPI registers. The number of data

bytes varies according to the register or memory being accessed.

The detailed data format diagram for continuous-mode

operation is given in the SPI Read/Write Data Formats section.

SPI ADDRESS DECODING

Table 11 shows the address decoding used in the SPI port. The

SPI address space encompasses a set of registers and the param-

eter RAM. The parameter RAM is loaded on power-up from an

on-board boot ROM.

Table 11. SPI Port Address Decoding

SPI Address

Read/Write Word Length

0–255

Parameter RAM Processor A

Write: 22 Bits, Read: 22 Bits

256

SPI Control Register Processor A

Write: 11 Bits, Read: N/A

257

Reserved

258

Output Level Processor A

Write: 22 Bits, Read: N/A

259

Stereo Spreading Control Processor A

Write: 22 Bits, Read: N/A

260

Dialog Enhancement Control Processor A

Write: 22 Bits, Read: N/A

512–767

Parameter RAM Processor B

Write: 22 Bits, Read: 22 Bits

768

SPI Control Register Processor B

Write: 22 Bits, Read: N/A

769

Reserved

770

Output Level Processor B

Write: 22 Bits, Read: N/A

771

Stereo Spreading Control Processor B

Write: 22 Bits, Read: N/A

772

Dialog Enhancement Control Processor B

Write: 22 Bits, Read: N/A

AD71028 Datasheet(PDF) 12 Page - Analog Devices

AD71028 Datasheet(HTML) 12 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Datasheet Download

Link URL