AD71028 datasheet(16/20 Pages) AD

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AD71028

Rev. 0 | Page 16 of 20

ANALOG OUTPUT SECTION

Figure 11 shows the block diagram of the analog output section

(one of two channels). A series of current sources is controlled

by a digital Σ-∆ modulator. Depending on the digital code from

the modulator, each current source is connected to the sum-

ming junction of either a positive I-to-V converter or a negative

I-to-V converter. Two extra current sources that push instead of

pull are added to set the midscale common-mode voltage.

All current sources are derived from the VREF input pin. The

gain of the AD71028 is directly proportional to the magnitude

of the current sources, and therefore the gain of the AD71028 is

proportional to the voltage on the VREF pin. The nominal

VREF voltage should be set to 2.5 V, using a simple resistive

divider from the analog supply. The VREF and biasing circuits

are common to both DACs.

IREF

IREF – DIG_IN

IREF + DIG_IN

SWITCHED CURRENT

SOURCES

BIAS

VREF IN

OUT–

OUT+

FROM DIGITAL

Σ–∆ MODULATOR

(DIG_IN)

Figure 11. Internal DAC Analog Architecture

Since the VREF input effectively multiplies the signal, care must

be taken to ensure that no ac signals appear on this pin. This

can be accomplished by using a large decoupling capacitor in

the VREF external resistive divider circuit. If the VREF signal is

derived by dividing the 5 V analog supply, the time constant of

the divider must effectively filter any noise on the supply. If the

VREF signal is derived from an unregulated power amplifier

supply, the time constant must be longer because the ripple on

the amplifier supply voltage will presumably be greater than in

the case of the 5 V supply.

The AD71028 should be used with an external third-order filter

on each output channel. The circuit shown in Figure 12

combines a third-order filter and a single-ended-to-differential

converter in the same circuit. The values shown are for a

100 kHz Bessel filter. The use of a Bessel filter is important to

maintain the time alignment of the pilot to the carrier. If these

signals are not in phase, a loss of separation will occur.

The outputs can also be used single-ended, with some loss of

performance; the DAC distortion may become significantly

poorer, although the SNR will remain quite high.

For best performance, a large (>10 µF) capacitor should be

connected between the FILTCAP pin and analog ground.

1.50k

Ω

2.7nF

499k

Ω

2.2nF

549

Ω

–INPUT

+INPUT

OUT

1nF

1.00k

Ω

3.01k

Ω

2.80k

Ω

806

Ω

820pF

270pF

Figure 12. Recommended External Analog Filter for Each Channel

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