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3.3

Device Configuration Controls

3.3.1

Channel Configuration Registers

TAS5508B

8-Channel Digital Audio PWM Processor

SLES162B – DECEMBER 2005 – REVISED APRIL 2006

The TAS5508B provides a number of system configuration controls that are set at initialization and

following a reset.

• Channel configuration

• Headphone configuration

• Audio system configurations

• Recovery from clock error

• Power-supply volume-control enable

• Volume and mute update rate

• Modulation index limit

• Master-clock and data-rate controls

• Bank controls

For the TAS5508B to have full control of the power stages, registers 0x05 to 0x0C must be programmed

to reflect the proper power stage and how each one should be controlled. There are eight channel

configuration registers, one for each channel. For information on using BKND_ERR and VALID, see

Section 3.2.3.1

The primary reason for using these registers is that different power stages require different handling

during start-up, mute/unmute, shutdown, and error recovery. The TAS5508B must select the sequence

that gives the best click and pop performance and ensures that the bootstrap capacitor is charged

correctly during start-up. This sequence depends on which power stage is present at the TAS5508B

output.

Table 3-5. Description of the Channel Configuration Registers (0x05 to 0x0C)

BIT

DESCRIPTION

Enable/disable error recovery sequence. In case the BKND_ERR pin is pulled low, this register determines if this channel is to

follow the error recovery sequence or to continue with no interruption.

Determines if the power stage needs the TAS5508B VALID pin to go low to reset the power stage. Some power stages can be

reset by a combination of PWM signals. For these devices, it is recommended to set this bit low, because the VALID pin is

shared for power stages. This provides better control of each power stage.

Determines if the power stage needs the TAS5508B VALID pin to go low to mute the power stage. Some power stages can be

muted by a combination of PWM signals. For these devices, it is recommended to set this bit low, because the VALID pin is

shared for power stages. This provides better control of each power stage.

Inverts the PWM output. Inverting the PWM output can be an advantage if the power stage input pin is opposite the TAS5508B

PWM pinout. This makes routing on the PCB easier. To keep the phase of the output, the speaker terminals must also be

inverted.

When using the TAS5182 power stage this bit must be set.

Can be used to handle click and pop for some applications.

This bit is normally used together with D2. For some power stages, both PWM signals must be high to get the desired operation

of both speaker outputs to be low. This bit sets the PWM outputs high-high during mute.

Not used

Table 3-6 lists the optimal setting for each output-stage configuration. Note that the default value is

applicable in all configurations except the TAS5182 SE/BTL configuration.

TAS5508B Controls and Status

TAS5508B Datasheet(PDF) 49 Page - Texas Instruments

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