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2.1.3

Terminal Descriptions

TAS5508B

8-Channel Digital Audio PWM Processor

SLES162B – DECEMBER 2005 – REVISED APRIL 2006

TERMINAL

5-V

TYPE(1)

TERMINATION(2)

DESCRIPTION

TOLERANT

NAME

NO.

AVDD_PLL

3.3-V analog power supply for PLL. This terminal can be connected to the same

power source used to drive power terminal DVDD; but to achieve low PLL jitter,

this terminal should be bypassed to AVSS_PLL with a 0.1-

µF low-ESR

capacitor.

AVSS

5, 6

Analog ground

AVSS_PLL

Analog ground for PLL. This terminal should reference the same ground as

terminal DVSS; but to achieve low PLL jitter, ground noise at this terminal must

be minimized. The availability of the AVSS terminal allows a designer to use

optimizing techniques such as star ground connections, separate ground planes,

or other quiet ground-distribution techniques to achieve a quiet ground reference

at this terminal.

BKND_ERR

Pullup

Active-low. A back-end error sequence is generated by applying logic low to this

terminal. The BKND_ERR results in no change to any system parameters, with

all H-bridge drive signals going to a hard-mute state (M-state).

DVDD

15, 36

3.3-V digital power supply. It is recommended that decoupling capacitors of

0.1

µF and 10 µF be mounted close to this pin (see application schematics).

DVDD_PWM

3.3-V digital power supply for PWM

DVSS

16, 34,

Digital ground

35, 38

DVSS_PWM

Digital ground for PWM

HP_SEL

5 V

Pullup

Headphone in/out selector. When a logic low is applied, the headphone is

selected (speakers are off). When a logic high is applied, speakers are selected

(headphone is off).

LRCLK

5 V

Serial-audio data left/right clock (sampling-rate clock)

MCLK

5 V

Pulldown

MCLK is a 3.3-V master clock input. The input frequency of this clock can range

from 4 MHz to 50 MHz.

MUTE

5 V

Pullup

Soft mute of outputs, active-low (muted signal = a logic low, normal operation =

a logic high). The mute control provides a noiseless volume ramp to silence.

Releasing mute provides a noiseless ramp to previous volume.

OSC_CAP

Oscillator capacitor

PDN

5 V

Pullup

Power down, active-low. PDN powers down all logic and stops all clocks

whenever a logic low is applied. The internal parameters are preserved through

a power-down cycle, as long as RESET is not active. The duration for system

recovery from power down is 100 ms.

PLL_FLT_RET

PLL external filter return

PLL_FLTM

PLL negative input. Connected to PLL_FLT_RET via an RC network

PLL_FLTP

PLL positive input. Connected to PLL_FLT_RET via an RC network

PSVC

Power-supply volume control PWM output

PWM_HPML

PWM left-channel headphone (differential –)

PWM_HPMR

PWM right-channel headphone (differential –)

PWM_HPPL

PWM left-channel headphone (differential +)

PWM_HPPR

PWM right-channel headphone (differential +)

PWM_M_1

PWM 1 output (differential –)

PWM_M_2

PWM 2 output (differential –)

PWM_M_3

PWM 3 output (differential –)

PWM_M_4

PWM 4 output (differential –)

PWM_M_5

PWM 5 output (lineout L) (differential –)

PWM_M_6

PWM 6 output (lineout R) (differential –)

PWM_M_7

PWM 7 output (differential –)

PWM_M_8

PWM 8 output (differential –)

PWM_P_1

PWM 1 output (differential +)

PWM_P_2

PWM 2 output (differential +)

PWM_P_3

PWM 3 output (differential +)

(1)

Type: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output

(2)

All pullups are 20-

µA weak pullups and all pulldowns are 20-µA weak pulldowns. The pullups and pulldowns are included to ensure

proper input logic levels if the terminals are left unconnected (pullups

→ logic-1 input; pulldowns → logic-0 input). Devices that drive

inputs with pullups must be able to sink 20

µA while maintaining a logic-0 drive level. Devices that drive inputs with pulldowns must be

able to source 20

µA while maintaining a logic-1 drive level.

Description

TAS5508B Datasheet(PDF) 18 Page - Texas Instruments

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