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TAS5508B Datasheet(PDF) 64 Page - Texas Instruments |
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TAS5508B Datasheet(HTML) 64 Page - Texas Instruments |
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64 / 106 page  www.ti.com 4.8.2 Left-Justified Timing 23 22 SCLK 32 Clks LRCLK Left Channel 24-Bit Mode 9 8 5 4 1 0 MSB LSB 23 22 32 Clks LRCLK Right Channel 9 8 5 4 1 0 MSB LSB 18 20-Bit Mode 5 4 1 0 19 14 16-Bit Mode 1 0 15 18 5 4 1 0 19 14 1 0 15 2-Channel Left-Justified Stereo Input T0034-02 TAS5508B 8-Channel Digital Audio PWM Processor SLES162B – DECEMBER 2005 – REVISED APRIL 2006 Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 64 fS is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK toggles. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5508B masks unused trailing data bit positions. Figure 4-11. Left-Justified 64-fS Format 64 Electrical Specifications |
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