3

T0353

4559AS–CDMA–10/02

Pin Configuration

Figure 2. Pinning

PLNA_GND

PLNA_IN

VCC_LNA

Gain

CLNA_OUT

CLNA_GND

CLNA_IN

GPS_LNA_IN

CDMA_OUT+

CDMA_OUT-

VCC_MIX

AMPS_OUT+

AMPS_OUT-

GPSMix_OUT+

GPSMix_OUT-

VCC_LO_TX

32 31 30 29 28 27 26 25

9 10 11 12 13 14 15 16

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

Pin Description

Pin

Symbol

Function

1PLNA_GND

PCS LNA emitter-ground. The LNA emitter ground should be grounded immediately to the ground-

plane to reduce stray inductance and capacitance that may affect performance.

2PLNA_IN

PCS LNA input. Requires a DC blocking capacitor and an L-C (shunt C/series L) matching network

for optimum gain, intercept and noise performance.

3

Vcc_LNA

Power supply pin for PCS and Cell LNAs. Bypass with a capacitor as close to the pin as possible.

4

Gain

Gain select logic input for cellular band. Logic high selects High Gain.

5CLNA_OUT

be used as part of the output matching network.

6CLNA_GND

Cell LNA emitter-ground. The LNA emitter ground should be grounded immediately to the ground-

plane to reduce stray inductance and capacitance that may affect performance.

7CLNA_IN

Cell LNA input. Requires a DC blocking capacitor and an L-C (shunt C/series L) matching network

for optimum gain, intercept and noise performance.

8

GPS_LNA_IN

GPS LNA input. Requires a DC blocking capacitor and an L-C (shunt C/series L) matching network

for optimum gain, intercept and noise performance.

9Iset_CELL

Bias resistor for Cell LNA. For typical bias use a 390

W resistor to ground which sets the bias

current for HGHL mode.

10

GPS_LNA_OUT

11

P_CLO_IN

PCS and Cell band LO input.

12

GLO_IN

GPS LO input.

13

LO / 2

LO divider-select input. Low disables divider. High selects divider in cellular and AMPS modes.

14

PLO_OUT

PCS LO buffer output. Internally matched to 100

W. Does not require a blocking capacitor.