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CS5535 Datasheet(PDF) 407 Page - National Semiconductor (TI) |
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CS5535 Datasheet(HTML) 407 Page - National Semiconductor (TI) |
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407 / 555 page ![]() Revision 0.8 407 www.national.com DMA Register Descriptions (Continued) Slave DMA Channel [3:0] Command (DMA_CH3:0_CMD) 5.13.2.4 Slave DMA Channel [3:0] Software Request (DMA_CH3:0_SFT_REQ) 5.13.2.5 Slave DMA Channel [3:0] Channel Mask (DMA_CH3:0_CHMSK) I/O Address 008h Type W Reset Value xxh DMA_CH3:0_CMD Register Map 76543 210 DACK_SENSE DREQ_SENSE WR_TIMING PR_MODE TM_MODE DMA_DIS RSVD DMA_CH3:0_CMD Bit Descriptions Bit Name Description 7 DACK_SENSE DACK Sense. 0: Active low; 1: Active high. 6 DREQ_SENSE DREQ Sense. 0: Active high; 1: Active low. 5 WR_TIMING Write Timing. 0: Late write; 1: Extended write. 4 PR_MODE Priority Mode. 0: Fixed priority; 1: Rotating priority. 3 TM_MODE Timing Mode. 0: Normal timing; 1: Compressed timing. 2DMA_DIS DMA Disable. 0: DMA enable for Channels [3:0]; 1: DMA disable for Channels [3:0]. 1:0 RSVD Reserved. Bit 0 must be written with value 0; bit 1 value is don’t care. I/O Address 009h Type WO Reset Value xxh DMA_CH3:0_SFT_REQ Register Map 76543 210 RSVD DMA_RQ DMA_CH_SEL DMA_CH3:0_SFT_REQ Bit Descriptions Bit Name Description 7:3 RSVD Reserved. Write value is don’t care. 2DMA_RQ DMA Request. Set to 1 to enable DMA request. 1:0 DMA_CH_SEL DMA Channel Select. 00: Channel 0. 10: Channel 2. 01: Channel 1. 11: Channel 3. I/O Address 00Ah Type WO Reset Value xxh DMA_CH3:0_CHMSK Register Map 76543 210 RSVD CH_MASK DMA_CH_SEL |
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