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CS5535 Datasheet(PDF) 408 Page - National Semiconductor (TI) |
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CS5535 Datasheet(HTML) 408 Page - National Semiconductor (TI) |
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408 / 555 page ![]() www.national.com 408 Revision 0.8 DMA Register Descriptions (Continued) 5.13.2.6 Slave DMA Channel [3:0] Mode (DMA_CH3:0_MODE) 5.13.2.7 Slave DMA Channel [3:0] Clear Byte Pointer (DMA_CH3:0_CLR_PNTR) DMA_CH3:0_CHMSK Bit Descriptions Bit Name Description 7:3 RSVD Reserved. Write value is don’t care. 2 CH_MASK Channel Mask. Set to 1 to mask out DMA for selected channel. 1:0 DMA_CH_SEL DMA Channel Select. 00: Channel 0. 10: Channel 2. 01: Channel 1. 11: Channel 3. I/O Address 00Bh Type WO Reset Value xxh DMA_CH3:0_MODE Register Map 76543 210 TRANS_MODE ADDR_DIR AUTO_INIT TRANS_TYPE DMA_CH_SEL DMA_CH3:0_MODE Bit Descriptions Bit Name Description 7:6 TRANS_MODE Data Transfer Mode. 00: Demand. 10: Block. 01: Single. 11: Cascade. 5 ADDR_DIR Address Direction. 0: Increment; 1: Decrement. 5 AUTO_INIT Auto-Initialization Enable. 0: Disabled; 1: Enabled. 3:2 TRANS_TYPE Transfer Type. 00: Verify. 10: Memory read. 01: Memory write. 11: Reserved 1:0 DMA_CH_SEL DMA Channel Select. 00: Channel 0. 10: Channel 2. 01: Channel 1. 11: Channel 3. I/O Address Offset 00Ch Type WO Reset Value xxh DMA_CH3:0_CLR_PNTR Register Map 76543 210 CLR_PNTR (DUMMY_VAL) |
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