Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

CS5535 Datasheet(PDF) 409 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # CS5535
Description  Geode??CS5535 I/O Companion Multi-Function South Bridge
PDF  555 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

CS5535 Datasheet(HTML) 409 Page - National Semiconductor (TI)

Back Button CS5535 Datasheet HTML 405Page - National Semiconductor (TI) CS5535 Datasheet HTML 406Page - National Semiconductor (TI) CS5535 Datasheet HTML 407Page - National Semiconductor (TI) CS5535 Datasheet HTML 408Page - National Semiconductor (TI) CS5535 Datasheet HTML 409Page - National Semiconductor (TI) CS5535 Datasheet HTML 410Page - National Semiconductor (TI) CS5535 Datasheet HTML 411Page - National Semiconductor (TI) CS5535 Datasheet HTML 412Page - National Semiconductor (TI) CS5535 Datasheet HTML 413Page - National Semiconductor (TI) Next Button
Zoom Inzoom in Zoom Outzoom out
 409 / 555 page
background image
Revision 0.8
409
www.national.com
DMA Register Descriptions (Continued)
5.13.2.8
Slave DMA Channel [3:0] Master Clear (DMA_CH3:0_MSTR_CLR)
5.13.2.9
Slave DMA Channel [3:0] Clear Mask Register (DMA_CH3:0_CLR_MSK)
5.13.2.10 Slave DMA Channel [3:0] Write Mask Register (DMA_CH3:0_WR_MSK)
DMA_CH3:0_CLR_PNTR Bit Descriptions
Bit
Name
Description
7:0
CLR_PNTR
Clear Pointer. A write with any data (dummy value) resets high/low byte pointer for
Channels 3:0 memory address and terminal count registers.
I/O Address
00Dh
Type
WO
Reset Value
xxh
DMA_CH3:0_MSTR_CLR Register Map
76543
210
MSTR_CLR (DUMMY_VAL)
DMA_CH3:0_MSTR_CLR Bit Descriptions
Bit
Name
Description
7:0
MSTR_CLR
Master Clear. A write with any data (dummy value) resets the 8237 DMA controller for
Channels [3:0].
I/O Address
00Eh
Type
WO
Reset Value
xxh
DMA_CH3:0_CLR_MSK Register Map
76543
210
CLR_MSK (DUMMY_VAL)
DMA_CH3:0_CLR_MSK Bit Descriptions
Bit
Name
Description
7:0
CLR_MSK
Clear Mask. A write with any data (dummy value) clears the mask bits for Channels
[3:0].
I/O Address
00Fh
Type
WO
Reset Value
0Fh
DMA_CH3:0_WR_MSK Register Map
76543
210
RSVD
CH3_MASK
CH2_MASK
CH1_MASK
CH0_MASK



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com