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CS5535 Datasheet(PDF) 454 Page - National Semiconductor (TI) |
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CS5535 Datasheet(HTML) 454 Page - National Semiconductor (TI) |
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454 / 555 page  www.national.com 454 Revision 0.8 GPIO Subsystem Register Descriptions (Continued) 5.16.3 GPIO Input Conditioning Function Registers The CS5535 has eight digital filter/event counter pairs (numbered 0 through 7) that can be shared with 28 GPIOs. There are two 16-bit registers associated with digital filter (FILTER_AMOUNT and FILTER_COUNTER) and two 16-bit registers associated with event counter (EVENTCOUNT and EVENT_COMP). The Input Conditioning Function registers are not based on the atomic programming model. 5.16.3.1 GPIO Filter Amount (GPIO_FLTR[x]_AMNT) GPIO_FILTER[x]_AMOUNT are 16-bit registers and programmed with a 16-bit filter count value. GPIO Filter 0 Amount (GPIO_FLTR0_AMNT) GPIO Filter 1 Amount (GPIO_FLTR1_AMNT) GPIO Filter 2 Amount (GPIO_FLTR2_AMNT) GPIO Filter 3 Amount (GPIO_FLTR3_AMNT) GPIO Filter 4 Amount (GPIO_FLTR4_AMNT) GPIO Filter 5 Amount (GPIO_FLTR5_AMNT) GPIO Filter 6 Amount (GPIO_FLTR6_AMNT) GPIO Filter 7 Amount (GPIO_FLTR7_AMNT) GPIO I/O Offset 50h Type R/W Reset Value 0000h GPIO I/O Offset 58h Type R/W Reset Value 0000h GPIO I/O Offset 60h Type R/W Reset Value 0000h GPIO I/O Offset 68h Type R/W Reset Value 0000h GPIO I/O Offset 70h Type R/W Reset Value 0000h GPIO I/O Offset 78h Type R/W Reset Value 0000h GPIO I/O Offset D0h Type R/W Reset Value 0000h GPIO I/O Offset D8h Type R/W Reset Value 0000h GPIO_FLTR[x]_AMNT Register Map 15 14 13 12 11 10 987 6543 210 FILTER_AMOUNT GPIO_FLTR[x]_AMNT Bit Descriptions Bit Name Description 15:0 FILTER_AMOUNT Filter Amount. The associated GPIO input must remain stable for a FILTER_AMOUNT number of 32 kHz clock edges in order for the output to change. A FILTER_AMOUNT of 0 effectively disables the filtering function because the counter will not roll over from 0 to all 1s. The maximum FILTER_AMOUNT is FFFFh. |
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