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CS5535 Datasheet(PDF) 477 Page - National Semiconductor (TI) |
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CS5535 Datasheet(HTML) 477 Page - National Semiconductor (TI) |
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477 / 555 page  Revision 0.8 477 www.national.com 5.18 POWER MANAGEMENT CONTROLLER REGISTER DESCRIPTIONS The registers for the Power Management Controller (PMC) are divided into four sets: • Standard GeodeLink Device MSRs (Shared with DIVIL, see Section 5.6.1 on page 299.) • PMC Specific MSRs • ACPI Registers • PM Support Registers The MSRs are accessed via the RDMSR and WRMSR pro- cessor instructions. The MSR address is derived from the perspective of the CPU Core. See Section 3.2 "CS5535 MSR Addressing" on page 53 for more details on MSR addressing. All MSRs are 64 bits, however, the PMC Specific MSRs (summarized in Table 5-66) are called out as 32 bits. The PMC module treats writes to the upper 32 bits (i.e., bits [63:32]) of the 64-bit MSRs as don’t cares and always returns 0 on these bits. The configuration registers associated with the PMC are divided into two categories: ACPI registers (summarized in Table 5-67) and PM Support registers (summarized in Table 5-68 on page 478): • The ACPI registers are accessed via Base Address Register, MSR_LBAR_ACPI (MSR 5140000Eh), as I/O Offsets. (See Section 5.6.2.7 on page 311 for bit descriptions of the Base Address Register.) • The PM Support registers are accessed via a Base Address Register, MSR_LBAR_PMS (MSR 5140000Fh), as I/O Offsets. (See Section 5.6.2.8 on page 312 for bit descriptions of the Base Address Register.) The reference column in the summary tables point to the page where the register maps and bit descriptions are listed. Table 5-66. PMC Specific MSRs Summary MSR Address Type Register Name Power Domain Reset Value Reference 51400050h R/W PMC Logic Timer (PMC_LTMR) Working 00000000h Page 479 51400051h R/W PMC Reserved (PMC_RSVD) No f/flops 00000000h Page 479 Table 5-67. ACPI Registers Summary ACPI I/O Offset Type Width (Bits) Register Name Power Domain Reset Value Reference 00h R/W 16 PM Status 1 (PM1_STS) (Note 1 and Note 2) Note 1. Required ACPI register. Note 2. Both PM1_STS and PM1_EN access Offset 00h when using 32-bit access. Only PM1_STS with a 16-bit access to Offset 00h. Only PM1_EN with a 16-bit access to Offset 02h. Offset 04h is reserved. Reads return 0. Standby 0000h Page 479 02h R/W 16 PM Enable 1 (PM1_EN) (Note 1 and Note 2) Standby 0100h Page 481 08h R/W 16 PM Control 1 (PM1_CNT) (Note 1 and Note 3) Note 3. SSMI may be implemented on this register by decode hardware outside of PM module. Working 0000h Page 481 0Ch R/W 16 PM Control 2 (PM2_CNT) (Note 4) Note 4. Optional ACPI register. SSMI may be implemented on this register by decode hardware outside of PM module. Working 0000h Page 482 10h RO 32 PM Timer (PM_TMR) (Note 1) Working 0000h Page 483 14h R/W 32 PM Reserved (PM_RSVD) No f/flops 0000h --- 18h R/W 32 General Purpose Events Status 0 (PM_GPE0_STS) (Note 5) Note 5. Required ACPI register that can also be implemented via a control method. Standby 00000000h Page 483 1Ch R/W 32 General Purpose Events Enable 0 (PM_GPE0_EN) (Note 5) Standby 00000000h Page 485 |
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