CS5535 datasheet(480/555 Pages) NSC

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PMC Register Descriptions (Continued)

PM1_STS Bit Descriptions

Bit

Name

Description

WAK_FLAG

(Note 1, Note 2)

Note 1. A wakeup event can come from any event enabled by PM1_EN (ACPI I/O Offset 02h) or PM_GPE0_EN (ACPI I/O

Offset 1Ch). A wakeup will occur even if the SCI is not mapped to an ASMI or IRQ.

Note 2. After starting a Sleep sequence, software would normally spin by entering a polling loop on the WAK_FLAG. This

bit is normally (software has cleared it from last Sleep) 0 before starting a Sleep sequence. The Sleep sequence

puts the processor in Suspend while it is spinning. When the sequence brings the processor out of Suspend, the

WAK_FLAG bit is set. The Sleep sequence starts when SLP_EN (ACPI I/O Offset 08h[13]) is written to a 1.

Wakeup Event Flag. This bit is set high by the hardware when any wakeup event

occurs. Write 1 to clear; writing 0 has no effect.

14:12

RSVD

Reserved. By convention write 0, but other values are “don’t care”. Reads always

return 0.

IGNORE

Ignore. By ACPI convention not used by software. Reads always return 0.

To support the Global Status Lock Flag bit, writing a 1 to this bit sets bit 5. Writing a 0

has no effect.

RTC_FLAG

Real-Time Clock Alarm Flag. This bit is set high by the hardware when the RTC gen-

erates an alarm. If RTC_EN (ACPI I/O Offset 02h[10]) is high, an SCI is generated.

Write 1 to clear; writing 0 has no effect.

SLPBTN_FLAG

Sleep Button Flag. This bit is set high by the hardware when the “sleep button” is

pushed. If SLPBTN_EN (ACPI I/O Offset 02h[9]) is high, an SCI is generated. Write 1

to clear; writing 0 has no effect.

8PWRBTN_FLAG

Power Button Flag. This bit is set high by the hardware when the “power button” is

pushed. If PWRBTN_EN (ACPI I/O Offset 02h[8]) is high, an SCI is generated. Write 1

to clear; writing 0 has no effect.

7:6

RSVD

Reserved. By convention write 0, but other values are “don’t care”. Reads always

return 0.

5GBL_FLAG

Global Lock Flag. If high, indicates that the BIOS released control of Global Lock Sta-

tus bit. This bit is cleared by writing a 1 to it. This bit is set by writing a 1 to bit 11

(IGNORE). If GLB_EN (ACPI I/O Offset 02h[5]) is high, an SCI is generated.

4BM_FLAG

Bus Master Flag. This bit indicates a master has requested the bus. Used to indicate a

possible incoherent cache when the processor is in state C3. This function is not sup-

ported because the CS5535 does not support the C3 state.

By convention write 0, but other values are “don’t care”. Reads return 0.

3:1

RSVD

Reserved. By convention write 0, but other values are “don’t care”. Reads always

return 0.

0TMR_FLAG

Timer Carry Flag. This bit is set high by the hardware anytime the Power Management

Timer rolls over from all 1s back to 0. If TMR_EN (ACPI I/O Offset 02h[0]) is high, an

SCI is generated when the rollover occurs. Write 1 to clear; writing 0 has no effect.

CS5535 Datasheet(PDF) 480 Page - National Semiconductor (TI)

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