PI7C8150AND datasheet(53/111 Pages) PERICOM

53 / 111 page

PI7C8150A

2-PORT PCI-TO-PCI BRIDGE

Page 53 of 111

APRIL 2006 – Revision 1.1

If the parity error response bit is set in the bridge control register, PI7C8150A does not

claim the transaction with S_DEVSEL_L; this may allow the transaction to terminate

in a master abort. If parity error response bit is not set, PI7C8150A proceeds normally

and accepts transaction if it is directed to or across PI7C8150A.

PI7C8150A sets the detected parity error bit in the secondary status register.

PI7C8150A asserts P_SERR_L and sets signaled system error bit in status register, if

both of the following conditions are met:

The SERR_L enable bit is set in the command register.

The parity error response bit is set in the bridge control register.

6.2

DATA PARITY ERRORS

When forwarding transactions, PI7C8150A attempts to pass the data parity condition from

one interface to the other unchanged, whenever possible, to allow the master and target

devices to handle the error condition.

The following sections describe, for each type of transaction, the sequence of events that

occurs when a parity error is detected and the way in which the parity condition is

forwarded across PI7C8150A.

6.2.1

CONFIGURATION WRITE TRANSACTIONS TO

CONFIGURATION SPACE

When PI7C8150A detects a data parity error during a Type 0 configuration write

transaction to PI7C8150A configuration space, the following events occur:

If the parity error response bit is set in the command register, PI7C8150A asserts

P_TRDY_L and writes the data to the configuration register. PI7C8150A also asserts

P_PERR_L. If the parity error response bit is not set, PI7C8150A does not assert

P_PERR_L.

PI7C8150A sets the detected parity error bit in the status register, regardless of the state of

the parity error response bit.

6.2.2

READ TRANSACTIONS

When PI7C8150A detects a parity error during a read transaction, the target drives data and

data parity, and the initiator checks parity and conditionally asserts PERR_L. For

downstream transactions, when PI7C8150A detects a read data parity error on the

secondary bus, the following events occur:

PI7C8150A asserts S_PERR_L two cycles following the data transfer, if the secondary

interface parity error response bit is set in the bridge control register.

06-0057

PI7C8150AND Datasheet(PDF) 53 Page - Pericom Semiconductor Corporation