PI7C8150AND datasheet(93/111 Pages) PERICOM

93 / 111 page

PI7C8150A

2-PORT PCI-TO-PCI BRIDGE

Page 93 of 111

APRIL 2006 – Revision 1.1

Bit

Function

Type

Description

Target Abort

during Posted

Write

R/WC

1: Signal P_SERR_L was asserted because the bridge received a

target abort when delivering post memory write data.

Reset to 0.

Master Abort

during Posted

Write

R/WC

1: Signal P_SERR_L was asserted because the bridge received a

master abort when attempting to deliver post memory write data

Reset to 0.

Delayed Write

Non-delivery

R/WC

1: Signal P_SERR_L was asserted because the bridge was unable to

deliver delayed write data after 2

24 attempts.

Reset to 0

Delayed Read –

No Data from

Target

R/WC

1: Signal P_SERR_L was asserted because the bridge was unable to

read any data from the target after 2

24 attempts.

Reset to 0.

Delayed

Transaction

Master Timeout

R/WC

1: Signal P_SERR_L was asserted because a master did not repeat a

read or write transaction before master timeout.

Reset to 0.

14.1.42

PORT OPTION REGISTER – OFFSET 74h

Bit

Function

Type

Description

Reserved

R/O

Reserved. Returns 0 when read. Reset to 0.

Primary MEMR

Command Alias

Enable

R/W

Controls PI7C8150A’s detection mechanism for matching memory

read retry cycles from the initiator on the primary interface

0: exact matching for non-posted memory write retry cycles from

initiator on the primary interface

1: alias MEMRL or MEMRM to MEMR for memory read retry

cycles from the initiator on the primary interface

Reset to 0

Primary MEMW

Command Alias

Enable

R/W

Controls PI7C8150A’s detection mechanism for matching non-posted

memory write retry cycles from the initiator on the primary interface

0: exact matching for non-posted memory write retry cycles from

initiator on the primary interface

1: alias MEMWI to MEMW for non-posted memory write retry

cycles from initiator on the primary interface

Reset to 0

Secondary

MEMR

Command Alias

Enable

R/W

Controls PI7C8150A’s detection mechanism for matching memory

read retry cycles from the initiator on the secondary

0: exact matching for memory read retry cycles from initiator on the

secondary interface

1: alias MEMRL or MEMRM to MEMR for memory read retry

cycles from initiator on the secondary interface

Reset to 0

06-0057

PI7C8150AND Datasheet(PDF) 93 Page - Pericom Semiconductor Corporation

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