MPQ3324

– 8-CH LED DRIVER WITH I2C AND PWM AND ANALOG DIMMING, AEC-Q100

MPQ3324 Rev. 1.0

MonolithicPower.com

11

2/18/2021

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© 2021 MPS. All Rights Reserved.

OPERATION

The MPQ3324 applies 8 internal current sources

in each LED string terminal. The LED current of

the channels are set via an external current-

setting resistor. The maximum current is 100mA.

Enable and Start-Up

When the input voltage exceeds the under-

voltage lockout (UVLO) threshold, and EN

exceeds the rising threshold, the MPQ3324

operates in standby mode, and the I2C is active.

After setting the I2C register, pull the EN bit high

to start up the system. The start-up sequence is

listed below:

1. VIN

2. EN

3. I2C setting

4. Set the EN bit

Channel Selection

Channels can be disabled by setting the

corresponding CHxEN (e.g. x = 1, 2, ..., 8) bit low,

or by connecting the channel to GND.

Dimming

Each channel has its own 6-bit analog dimming

register and 12-bit PWM dimming register. The

MPQ3324 can use analog dimming and PWM

dimming for each channel.

In analog dimming, the LED current amplitude

changes when the analog dimming register

changes. Change the ICHx (e.g. x = 1, 2, ..., 8)

bit to set analog dimming for the corresponding

channel. The LED current (ILED) can be estimated

with Equation (1):

LED

ICHx

I

ISET

63



(1)

Where ICHx sets the analog dimming code for

the channel. If ICHx = 0, ILED is 0A.

In PWM dimming, the LED current is a PWM

waveform. The LED current amplitude stays the

same, and the LED current duty varies with the

PWM dimming register.

The PWM dimming duty is set by PWMx (e.g. x

= 1, 2, ..., 8). The duty (D) can be calculated with

Equation (2):

PWMx

D

4095



(2)

Where PWMx is the PWM dimming duty code for

each corresponding channel. The duty changes

only when the 8MSB of the PWM duty register is

written. When PWMx = 0, the corresponding ILED

is 0A.

The PWM dimming frequency can be selected

via register FPWM1:0. The potential frequencies

are listed below:

 FPWM1:0 = 00: 220Hz

 FPWM1:0 = 01: 250Hz (default)

 FPWM1:0 = 10: 280Hz

 FPWM1:0 = 11: 330Hz

To avoid a glitch during normal operation, the

following conditions must be met:

 Change the FPWM1:0 value only when the

EN bit is set 0.

 Write the FPWM register and wait for a 10µs

delay before writing to other registers.

Phase Shift

A channel-by-channel phase shift function can

be implemented. This function is enabled by

setting the PS_EN bit high.

When the phase shift function is enabled, the

channel x + 1 (e.g. x = 1, 2, ..., 7) LED current

rising edge is delayed for 80

μs after channel x’s

LED current rising edge.

SYNC Output for the LCD Refresh Frequency

The fault indicator function can be enabled by

the FLTEN bit.

If FLTEN = 0, the fault indicator function is

disabled.

RFSH/FLT

maintains

the

output

refresh signal, even if a protection is triggered.

If FLTEN = 1, the fault indicator function is

enabled, and the RFSH/FLT pin is pulled low if a

protection occurs. Table 1 shows the details of

the RFSH/FLT pin

’s output status.