MPQ3324

– 8-CH LED DRIVER WITH I2C AND PWM AND ANALOG DIMMING, AEC-Q100

MPQ3324 Rev. 1.0

MonolithicPower.com

13

2/18/2021

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VIN Under-Voltage Lockout (UVLO)

If the input voltage drops to the VIN UVLO

threshold, the IC stops working, and all I2C

registers are reset.LED Open-Load Protection

If an LED open fault occurs, the LEDx (e.g. x =

1, 2, ..., 8) voltage drops. If the LEDx voltage

drops below the protection threshold (about

100mV) for 4ms, LED open-load protection is

triggered. Once this occurs, the fault channel

turns off, the corresponding CHxO (x = 1, 2, ...,

8) open fault bit is set, and the RFSH/FLT pin is

pulled low. The fault bit is reset when it is read,

and the RFSH/FLT pin is pulled high.

LED Short Protection

If an LED short condition occurs, the VIN -

VLEDx voltage drops. If the VLEDx (e.g. x = 1,

2, ..., 8) voltage exceeds the voltage set by STH

for 4ms, LED short protection is triggered. Once

this occurs, the short channel turns off, the

corresponding CHxS fault bit is set, and

RFSH/FLT pulls low.

The LED short protection threshold is configured

by STH1:0, and can be set to the following

values:

 STH1:0 = 00: 2V

 STH1:0 = 01: 3V

 STH1:0 = 10: 4V

 STH1:0 = 11: 5V

The fault bit is reset when it is read, and the

RFSH/FLT pin is pulled high.

Over-Temperature Protection (OTP)

If the IC temperature exceeds 170°C, over-

temperature protection (OTP) is triggered. All

channels turn off, the RFSH/FLT pin is pulled low,

and the FT_OTP bit is set. If the temperature

drops by 20°C, the IC recovers, all channels turn

on, and the part resumes normal operation.

I2C Interface Register

I2C Chip Address

The device

’s address is 0x30~0x39, and is

configured by the ADDR resistor. The internal

current source flows to the ADDR resistor, then

the voltage of ADDR determines the I2C address.

10 different addresses can be configured

through the ADDR resistor. Table 2 shows how

the relationship between I2C address and

resistor ratio the (RADDR / RISET).

Table 2: I2C Address Setting

RADDR / RISET

I2C Address

(A3, A2, A1, A0)

<0.05

0000

>0.05, <0.15

0001

>0.15, <0.25

0010

>0.25, <0.35

0011

>0.35, <0.45

0100

>0.45, <0.55

0101

>0.55, <0.65

0110

>0.65, <0.75

0111

>0.75, <0.85

1000

>0.85, <0.95

1001

At start-up, the IC checks the I2C address first.

This address remains the same during normal

operation

, unless the IC’s power is reset.

After the start condition, the I2C-compatible

master sends a 7-bit address followed by an 8th

read (1) or write (0) bit. The 8th bit indicates the

register address to/from which the data will be

written/read (see Figure 6).

0

A0

1

1

A3

A1

R/W

A2

Figure 6: The I2C-Compatible Device Address

To avoid a glitch during normal operation, ensure

that the following conditions are met:

 Change the FPWM1:0 value only when the

EN bit is set to 0.

 Write the FPWM register and wait for a 10µs

delay before writing other registers.