IR2159 datasheet(20/25 Pages) IRF

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IR2159/IR21591 (S)

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Once lock is achieved, the phase detector (PDET)

outputs short pulses to an open-drain PMOS that

charges the VCO capacitor through an internal

resistor (RFB) each time an error pulse occurs

(Figure 12).This action "nudges" the integrator at

the input of the VCO to keep the phase of the

output stage current exactly locked in phase with

the reference.

REF

VCO

ERR

Figure 12, Phase control timing diagram.

The IR2159 includes a dimming interface for

analog lamp power control. The DIM pin input

requires a voltage in the range of 0.5 to 5VDC,

with 5V corresponding to minimum phase shift

(maximum lamp power). The output of the dim

interface is the voltage on pin MIN, which is

compared with the internal timing capacitor (CT)

voltage to produce a frequency-independent digital

reference phase (Figure 13).

0.5V

5 V

MIN

DIM

MIN

MAX

USER

SETTING

DIM

RANGE

-90

-180

REF

Figure 13, Dimming interface

The charging time of CT from 1V to 5.1V

determines the on-time of output gate drivers HO

and LO and corresponds to -180 degrees of

possible phase shift in load current (minus

deadtime). For the 0 to -90 degree dim range, the

voltage on pin MIN is bounded between 1V and

3V using pins MIN and MAX. An external resistor

on pin MAX programs the minimum phase shift

reference (maximum lamp power) corresponding

to 5V on pin DIM, and an external resistor on pin

MIN sets the maximum phase shift (minimum

lamp power) corresponding to 0.5V on pin DIM.

Current Sensing

During dimming, the current sensing circuitry

(Figure 14) detects over-current which can occur

during hard-switching (see Fault section), and

zero-crossing to measure the phase of the total

load current. To reject any switching noise which

can occur at the turn-on of the low-side MOSFET

or IGBT, a digital current sense blanking circuit

blanks out the signal from the zero-crossing

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