MCP19116 datasheet(77/246 Pages) MICROCHIP

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DS20005479D-page 77

MCP19116/7

10.5.2

SYNCHRONOUS SLAVE RECEIVE

MODE

The operation of the Synchronous Master and Slave

modes is identical, except in the case of the Sleep

mode. Bit SREN is a “don't care” in Slave mode.

If receive is enabled by setting bit CREN prior to the

SLEEP instruction, then a word may be received

during Sleep. On completely receiving the word, the

RSR register will transfer the data to the RCREG reg-

ister and if enable bit RCIE bit is set, the interrupt gen-

erated will wake the chip from Sleep. If the global

interrupt is enabled, the program will branch to the

interrupt vector (0004h).

When setting up a Synchronous Slave Reception, fol-

low these steps:

Enable the synchronous master serial port by

setting bits SYNC and SPEN and clearing bit

CSRC.

If interrupts are desired, set enable bit RCIE.

If 9-bit reception is desired, set bit RX9.

To enable reception, set enable bit CREN.

Flag bit RCIF will be set when reception is com-

plete and an interrupt will be generated, if

enable bit RCIE was set.

Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

Read the 8-bit received data by reading the

RCREG register.

If any error occurred, clear the error by clearing

bit CREN.

If using interrupts, ensure that GIE and PEIE

(bits 7 and 6) of the INTCON register are set.

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