Preliminary Data Sheet

AD45335

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. PrA | 9 of 17

Table 5. Pin Function Descriptions (Continued)

Mnemonic

Description

SCLK

Serial Clock Input. Data is clocked into the shift register upon the falling edge of SCLK. The pin operates at clock speeds of up to 30 MHz. Internal pull-up

device on logic input; therefore, it can be left floating and defaults to a logic high condition.

DIN

Serial Data Input. Data must be valid upon the falling edge of SCLK.

TEST

For normal operation, tie this pin low.

RESET

Active Low Input. This pin can also be used to reset the complete device to its power-on reset conditions. Zero code is loaded to the DACs.

NC

No Connect. Do not connect to these pins.