UPD17062 datasheet(174/298 Pages) RENESAS

174 / 298 page

172

µPD17062

14.2

RESET FUNCTION

Power-on reset is applied when VDD rises from a certain voltage, CE reset is applied when the CE pin rises

from low level to high level.

Power-on reset initializes the program counter, stack, system register and control registers, and executes

the program from address 0000H.

CE reset initializes the program counter, stack, system register and some control registers, and executes

the program from address 0000H.

The main differences between power-on reset and CE reset are the operation of the control registers that

are initialized and the power failure detection circuit described in Section 14.6.

Power-on reset and CE reset are controlled by reset signals IRES, RES, and RESET output from the reset

control circuit in Fig. 14-1.

Table 14-1 shows the IRES, RES, and RESET signal and power-on reset and CE reset relationship.

The reset control circuit also operates when the clock-stop instruction (STOP) described in Chapter 13 is

executed.

Sections 14.3 and 14.4 describe CE reset and power-on reset, respectively.

Section 14.5 describes the relationship between CE reset and power-on reset.

Table 14-1

Relationship between Internal Reset Signal and Each Reset

Output signal

Internal reset signal

At CE reset

At power-

At clock-stop

Contents controlled by each reset signal

on reset

IRES

Forces the device into the halt state.

The halt state is released by the setting of the

timer carry FF.

RES

Initializes some control registers.

RESET

Initializes the program counter, stack, system

UPD17062 Datasheet(PDF) 174 Page - Renesas Technology Corp