Electronic Components Datasheet Search
  English  ▼

X  

UPD17062 Datasheet(PDF) 175 Page - Renesas Technology Corp

Part # UPD17062
Description  MOS INTEGRATED CIRCUIT
PDF  298 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

UPD17062 Datasheet(HTML) 175 Page - Renesas Technology Corp

Back Button UPD17062 Datasheet HTML 171Page - Renesas Technology Corp UPD17062 Datasheet HTML 172Page - Renesas Technology Corp UPD17062 Datasheet HTML 173Page - Renesas Technology Corp UPD17062 Datasheet HTML 174Page - Renesas Technology Corp UPD17062 Datasheet HTML 175Page - Renesas Technology Corp UPD17062 Datasheet HTML 176Page - Renesas Technology Corp UPD17062 Datasheet HTML 177Page - Renesas Technology Corp UPD17062 Datasheet HTML 178Page - Renesas Technology Corp UPD17062 Datasheet HTML 179Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 175 / 298 page
background image
173
µPD17062
14.3
CE RESET
CE reset is executed by raising the CE pin from low level to high level.
When the CE pin rises to high level, the RESET signal is output and the device is reset in synchronization
with the rising edge of the pulse used for the next setting of the timer carry FF.
When CE reset is applied, the RESET signal initializes the program counter, stack, system register, and some
control registers to their initial value and executes the program from address 0000H.
For the initial values, see the relevant item.
CE reset operation is different when clock-stop is used and when it is not used.
These operations are described in Sections 14.3.1 and 14.3.2, respectively.
Section 14.3.3 describes the cautions at CE reset.
14.3.1
CE Reset When Clock-Stop (STOP Instruction) Not Used
Fig. 14-2 shows the reset operation.
When clock-stop (STOP instruction) is not used, the timer mode selection register of the control registers
is not initialized.
Therefore, after the CE pin becomes high level, the RESET signal is output, and reset is applied at the rising
edge of the timer carry FF set pulse (5 or 100 ms) .
Fig. 14-2
CE Reset Operation When Clock-Stop Not Used
5 V
0 V
Normal operation
Normal
operation
XOUT
VDD
CE
Timer carry FF
set pulse
IRES
RES
RESET
CE reset is applied at the rising
edge of the timer carry FF set pulse.
This period, t, varies with the timing when
the CE pin signal rises. It falls in the range
from 0 to tSET (0 < t < tSET), which is the
selected set time of the timer carry FF .
The program continues to run during this
period.
"H"
"H"



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com