UPD17062 datasheet(176/298 Pages) RENESAS

176 / 298 page

174

µPD17062

14.3.2

CE Reset When Clock-Stop (STOP Instruction) Used

Fig. 14-3 shows the reset operation.

When clock-stop is used, the IRES, RES and RESET signals are output at the time the STOP instruction is

executed.

At this time, the RES signal initializes the timer mode selection register of the control registers to 0000B

and sets the timer carry FF set signal to 100 ms.

Since the IRES signal is output continuously while the CE pin is low level, release by timer carry FF is forcibly

halted.

Since the clock itself stops, the device stops operating.

When the CE pin rises to high level, the clock-stop state is released and oscillation begins.

The IRES signal halts release by timer carry FF. When the timer carry FF set pulse rises after the CE pin

rises, the halt state is released and the program starts from address 0.

Since the timer carry FF set pulse is initialized to 100 ms, CE reset is applied 50 ms after the CE pin rises

to high level.

Fig. 14-3

CE Reset Operation When Clock-Stop Used

5 V

0 V

Normal operation

Clock-stop state

XOUT

VDD

Timer carry FF

set pulse

IRES

RES

RESET

CE reset

Program starts from address 0.

Clock stop release

Oscillation start

STOP

0000B

Halt state

50 ms

UPD17062 Datasheet(PDF) 176 Page - Renesas Technology Corp