AM69 datasheet(5/300 Pages) TI1

5 / 300 page

Table of Contents

1 Features............................................................................1

2 Applications..................................................................... 2

3 Description.......................................................................3

3.1 Functional Block Diagram........................................... 3

4 Revision History.............................................................. 5

5 Device Comparison......................................................... 7

6 Terminal Configuration and Functions........................10

6.1 Pin Diagrams............................................................ 10

6.2 Pin Attributes.............................................................10

6.3 Signal Descriptions................................................... 87

6.4 Pin Connectivity Requirements...............................131

7 Specifications.............................................................. 136

7.1 Absolute Maximum Ratings.................................... 136

7.2 ESD Ratings........................................................... 137

7.3 Power-On-Hour (POH) Limits................................. 138

7.4 Recommended Operating Conditions.....................138

7.5 Operating Performance Points................................140

7.6 Electrical Characteristics.........................................141

7.7 VPP Specifications for One-Time Programmable

(OTP) eFuses............................................................147

7.8 Thermal Resistance Characteristics....................... 149

7.9 Temperature Sensor Characteristics.......................150

7.10 Timing and Switching Characteristics................... 151

8 Detailed Description....................................................269

8.1 Overview................................................................. 269

8.2 Functional Block Diagram....................................... 269

8.3 Processor Subsystems........................................... 271

8.4 Accelerators and Coprocessors..............................272

8.5 Other Subsystems.................................................. 273

9 Applications, Implementation, and Layout............... 282

10 Device Connection and Layout Fundamentals.......283

10.1 Power Supply Decoupling and Bulk Capacitors....283

10.2 External Oscillator.................................................283

10.3 JTAG and EMU..................................................... 283

10.4 Reset.....................................................................283

10.5 Unused Pins..........................................................283

10.6 Hardware Design Guide for JacintoTM 7 Devices. 283

11 Peripheral- and Interface-Specific Design

Information.................................................................. 284

11.1 LPDDR4 Board Design and Layout Guidelines.... 284

11.2 OSPI and QSPI Board Design and Layout

Guidelines................................................................. 284

11.3 USB VBUS Design Guidelines..............................287

11.4 System Power Supply Monitor Design

Guidelines using VMON/POK................................... 288

11.5 High Speed Differential Signal Routing Guidance 289

11.6 Thermal Solution Guidance...................................289

12 Device and Documentation Support........................290

12.1 Device Nomenclature............................................290

12.2 Tools and Software............................................... 293

12.3 Support Resources............................................... 293

12.4 Trademarks...........................................................293

12.5 Electrostatic Discharge Caution............................293

12.6 Glossary................................................................293

13 Mechanical, Packaging, and Orderable

Information.................................................................. 294

13.1 Packaging Information.......................................... 294

4 Revision History

Changes from March 2, 2023 to August 18, 2023 (from Revision * (MARCH 2023) to Revision A

(AUGUST 2023))

Page

• Global: Updated/Changed document title from "AM69Ax" to "AM69x"......................................................... 0

• Global:: Deleted all OLDI/LVDS content; n/a to this device suite...................................................................... 1

• Global: Updated/Changed "BSX", "BSX-64-4", and "BXS-64-4" to "IMG BXS-4-64" for the 3D Graphics

Processing Unit (GPU)....................................................................................................................................... 1

• (Package Information): Updated the table to match the new content standard..................................................3

• (Device Comparison): Added AM69 and AM69A part numbers to the table. Merged table cells to show

commonality/differences and to improve readability........................................................................................... 7

• (Device Comparison): Added software build sheet Note.................................................................................... 7

• (Device Comparison): Added footnotes to clarify LPDDR instance usage for a) pin compatibility with 27 mm

package, and b) requirements for using fewer than 4 DDR instances............................................................... 7

• (DDRSS0 Signal Descriptions): Added "DDRSS incremental order" footnote................................................. 88

• (DDRSS1 Signal Descriptions): Added "DDRSS incremental order" footnote................................................. 89

• (DDRSS2 Signal Descriptions): Added "DDRSS incremental order" footnote................................................. 91

• (DDRSS2 Signal Descriptions): Added DDRSS2, DDRSS3, and SERDES2 availability footnote................... 91

• (DDRSS3 Signal Descriptions): Added "DDRSS incremental order" footnote................................................. 92

• (DDRSS3 Signal Descriptions): Added DDRSS2, DDRSS3, and SERDES2 availability footnote................... 92

• (SERDES2 Signal Descriptions): Added DDRSS2, DDRSS3, and SERDES2 availability footnote............... 113

• (Pin Connectivity Requirements) Updated ADC AIN recommendation to allow the tie-off of signals directly to

ground.............................................................................................................................................................131

• (Pin Connectivity Requirements): Added requirement for DDR interfaces to be used in incrementing order 131

www.ti.com

AM69A, AM69

SPRSP92A – FEBRUARY 2023 – REVISED AUGUST 2023

Submit Document Feedback

Product Folder Links: AM69A AM69

AM69 Datasheet(PDF) 5 Page - Texas Instruments

AM69 Datasheet(HTML) 5 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL