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Over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOL

Output Low Voltage

0.4

VOH

Output High Voltage

2.4

IOL

Low Level Output Current

VOL(MAX)

IOH

High Level Output Current

VOH(MIN)

(1)

VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see the Pin

Attributes, POWER column.

7.6.9 USB2PHY Electrical Characteristics

Note

USB0 and USB1 Electrical Characteristics are compliant with Universal Serial Bus Revision 2.0

Specification dated April 27, 2000 including ECNs and Errata as applicable.

7.6.10 SerDes 2-L-PHY/4-L-PHY Electrical Characteristics

Note

The PCIe interfaces are compliant with the electrical parameters specified in PCI Express® Base

Specification Revision 4.0, September 27, 2017.

This Device imposes an additional limit on SERDES REFCLK when used in Input mode with internal

termination enabled, as described by parameter VREFCLK_TERM in Table 7-2, 4-L-PHY SERDES

REFCLK Electrical Characteristics. Internal termination is enabled by default and must be disabled

before applying a reference clock signal that exceeds the limits defined by VREFCLK_TERM. External

termination should always be enabled on the source side.

Table 7-2. 4-L-PHY SERDES REFCLK Electrical Characteristics

Only applies when internal termination is enabled. Over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

TYP

MAX

UNIT

VREFCLK_TER

Single ended voltage threshold at the reference clock

pin when internal termination is enabled

400

RTERM

Internal termination

62.5

Note

The SerDes USB interfaces are compliant with the USB3.1 SuperSpeed Transmitter and Receiver

Normative Electrical Parameters as defined in the Universal Serial Bus 3.1 Specification, Revision

1.0 , July 26, 2013.

Note

The SGMII interfaces electrical characteristics are compliant with 1000BASE-KX per IEEE802.3

Clause 70.

Note

The SGMII 2.5G / XAUI interfaces electrical characteristics are compliant with IEEE802.3 Clause 47.

Note

The QSGMII interface electrical characteristics are compliant with QSGMII Specification revision 1.2.

AM69A, AM69

SPRSP92A – FEBRUARY 2023 – REVISED AUGUST 2023

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