MPQ8112/MPQ8112A

– 60V, HIGH-SIDE, CURRENT-SENSE AMPLIFIER

MPQ8112/MPQ8112A Rev. 1.0

www.MonolithicPower.com

4

7/7/2020

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

© 2020 MPS. All Rights Reserved.

PIN FUNCTIONS

Pin #

Name

Description

1

OUT

Output. The MPQ8112 does not require an external resistor, so the OUT pin can be left

floating. For the MPQ8112A, connect an external resistor to OUT to set the gain.

2

RG2

Negative gain resistor. For the MPQ8112, connect RG2 directly to the load side of the

current-sense resistor, as closely as possible. For the MPQ8112A, connect RG2 to the load

side of the current-sense resistor through a gain resistor (RG2). RG2 should be below 4k

Ω to

obtain high current-sense accuracy. It is recommended for RG2 and RG1 to equal 1k

Ω.

3

RG1

Positive gain resistor. For the MPQ8112, connect RG1 directly to the power side of the

current-sense resistor, as closely as possible. For the MPQ8112A, connect RG1 to the

power side of the current-sense resistor through a gain resistor (RG1). RG1 should be below

4k

Ω to obtain the high current-sense accuracy. It is recommended for RG1 to equal 1kΩ.

4

VCC

Power input. Place a bypass capacitor between VCC and GND, as close as possible. A

0.1µF to 1µF low-ESR ceramic capacitor is recommended.

5

GND

Ground.

6

V5

Power supply for internal trim and control block. Pull V5 above its 2V upper threshold to

enable the part. Pull V5 below its 1.9V lower threshold to disable the part. The power

source connected to V5 must be able to output a current above 1mA. Place a bypass

capacitor between V5 and GND. A 10nF to 100nF low-ESR ceramic capacitor is

recommended.

ABSOLUTE MAXIMUM RATINGS (1)

VCC to GND ..................................-0.3V to +62V

RG1, RG2 to GND ......................... -0.3V to VCC

VCC to RG1, RG2 .........................-0.3V to +62V

OUT to GND ............ -0.3V to +22V (MPQ8112)

OUT to GND ............ -0.3V to VCC (MPQ8112A)

Differential input voltage (VRG1 - VRG2)... ±400mV

V5 to GND .....................................-0.3V to +6V

Max junction temperature .........................150°C

Storage temperature ................ -65°C to +150°C

Continuous power dissipation (TA = 25°C) (2)

TSOT23-6L .............................................. 0.57W

ESD Ratings (3)

Human body model (HBM).........................±2kV

Charged device model (CDM)..................±750V

Recommended Operating Conditions

Vcc to GND ...................................... 2.7V to 60V

RG1, RG2 to GND ...............................0V to VCC

VCC to RG1, RG2 ...............................0V to 60V

OUT to GND ................... 0V to 20V (MPQ8112)

OUT to GND ....... 0V to VCC - 0.7V (MPQ8112A)

Operating junction temp (TJ)..............................

………………………………...-40°C to +125°C (4)

Thermal Resistance (5)

θJA

θJC

TSOT23-6L ............................ 220 .... 110.. °C/W

Notes:

1) Exceeding these ratings may damage the device.

2) The maximum allowable power dissipation is a function of the

maximum junction temperature, TJ (MAX), the junction-to-

ambient thermal resistance,

θ

JA, and the ambient temperature,

TA. The maximum allowable continuous power dissipation at

any ambient temperature is calculated by PD (MAX) = (TJ

(MAX) - TA) / θJA. Exceeding the maximum allowable power

dissipation will cause excessive die temperature, and the

regulator will go into thermal shutdown. Internal thermal

shutdown circuitry protects the device from permanent

damage.

3) These devices are ESD-sensitive. It is recommended to

handle them with precaution.

4) It is possible to operate the devices at junction temperatures

above 125°C. Contact an MPS FAE for details.

5)

The value of θ

JA given in this table is only valid for comparison

with other packages and cannot be used for design purposes.

These values were calculated in accordance with JESD51-7,

and simulated on a specified JEDEC board. They do not

represent the performance obtained in an actual application.