ES9080 datasheet(132/146 Pages) ESS

132 / 146 page

CONFIDENTIAL ADVANCE INFORMATION 0.4.3

ES9080 Product Datasheet

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM

132

Addendum

The following subsections outline the recommended configuration for common I2S and TDM modes in s2m format.

I2S Master

//Initialize into I2S with 4 data lines (8 channel), MCLK = 49.152MHz, fs = 48kHz, DRE

enabled, automute enabled

w 0x98 192 0x03; //Set GPIO1 (MCLK) pad to input mode, Invert CLKHV phase for better DNR

w 0x98 193 0xC3; //Set PLL Bypass, Remove 10k DVDD shunt to ground, set PLL input to MCLK,

enable the PLL clock inputs

w 0x98 202 0x40; //Set PLL Parameters

w 0x90 1 0xFF;

//Enable Interpolation and modulator clocks for all 8 channels

w 0x90 2 0x01;

//Enable the TDM decoder

//This sets the MCLK/FS rate

//w 0x90 3 0x00;

//128FS Eg, 49.152MHz/384kHz

//w 0x90 4 0x00;

//128FS Eg, 49.152MHz/384kHz

//w 0x90 3 0x01;

//256FS Eg, 49.152MHz/192kHz

//w 0x90 4 0x01;

//256FS Eg, 49.152MHz/192kHz

//w 0x90 3 0x03;

//512FS Eg, 49.152MHz/96kHz

//w 0x90 4 0x03;

//512FS Eg, 49.152MHz/96kHz

w 0x90 3 0x07;

//1024FS Eg, 49.152MHz/48kHz

w 0x90 4 0x07;

//1024FS Eg, 49.152MHz/48kHz

w 0x90 5 0xFF;

//Enable all 8 channels Analog section.

w 0x90 6 0x1F;

//Set the PNEG charge pump clock frequency to 705.6kHz or 768kHz

(depending on MCLK being 22.5792MHz or 24.576MHz)

w 0x90 7 0xBB;

//Setup automated delay sequence for analog section quietest pop

w 0x90 51 0x80;

//Force a PLL_LOCKL signal from analog since it it bypassed to prevent

muting the DAC automatically

//GPIO Registers

w 0x90 62 0x0E;

//Enable GPIO2/3/4 Inputs

ES9080 Datasheet(PDF) 132 Page - ESS Technology,Inc

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