RHR801

Parameters and implementation

5.3

Characteristics of the output stage

The RHR801 uses a rail-to-rail MOS output. The output levels are guaranteed through

testing (see the output characteristics in Table 4 and Table 5). This stage is optimized for

driving a load of 1

kΩ, with no stability issues. The capacitive load affects both the rise and

fall times.

5.4

Impedance matching for dynamic measurements

To correctly evaluate this high-speed comparator, both the input and output must be

properly matched (50

Ω). This matching is mandatory to avoid reflections on the tracks and

cables, particularly at such high-speed rise and fall times. The matching of the input is

relatively easy to perform with a 50

Ω input resistance placed as close as possible to the

comparator input. The input track is 50

Ω matched. For the output, the comparator cannot

drive a 50

Ω line directly. So, to reduce the output current while keeping a good 50 Ω

termination on both sides of the cable, it is mandatory to use a series resistor much greater

than 50

Ω, for example, 1 kΩ as in Figure 39.

Figure 39: Output impedance matching

5.5

Implementation on the board

The RHR801 is a very high-speed product that features very sharp output rise and fall

times. The very high current variations must be appropriately managed and proper board

layout techniques should be used to ensure best performances.

It is important to minimize the resistance from the source to the input of the comparator.

High resistance values combined with the equivalent input capacitance can result in time

constants below the capability of the comparator. This is the cause of a lagged response at

the input, resulting in an output delay. Moreover, proper ground impedance and other

layout techniques must be implemented to minimize the input stray capacitance, such as

very short tracks on any high-impedance termination.

With high-speed applications, it is very important to provide bypass capacitors for the

power supply. Good power supply decoupling is mandatory (pin 4 and pin 7), as well as

good decoupling on the reference (pin 2). With dual supplies, a 10 µF bypass capacitor

should be placed on each power supply pin. This capacitor reduces any potential voltage

ripple from the power supply at lower frequencies. A 10 nF ceramic capacitor should be

placed as close as possible to the power supply pins and be tracked to ground. This

capacitor reduces higher frequency noise during high-frequency switching.

A proper ground plane is particularly recommended for high-speed performance. It can be

created by implementing a continuous conductive plane all over the surface of the circuit

board, with breaks for the necessary paths only. A proper ground plane minimizes the

effects of stray capacitance on the circuit board and facilitates the layout of matched tracks.

50

Capa-load

Vin

Fin

+

_

RHR801

50

1 k

To reduce output current

Vcc = +3V/+5 V

Very short track

50

track

50

50

termination

V-reference

10 F

10 F

10 nF

Ω

µ

Ω

Ω

µ

Ω

Ω

Ω

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