P3041 Multicore Processing Options

P3041 QorIQ Communications Processor Product Brief, Rev. 0

Freescale Semiconductor

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P3041 Multicore Processing Options

The four P3041 cores can run either on an OS or run OS-less using a simple scheduler.

2.1

Running on an OS

There are different multi-processing options with the P3041 cores running on an OS:

•

Four-core, asymmetric

— Four copies of the same uni-processor operating system

or

— Up to four different uni-processor operating systems

•

Four-core, symmetric

•

Mixed symmetric and asymmetric For example, N cores running in SMP mode, while the

remainder of the cores operate asymmetrically with up to 4–N different OSes

2.2

Running OS-Less Using a Simple Scheduler

Running one or more cores OS-less using a simple scheduler is a likely use case when cores are performing

datapath operations with bounded real-time requirements. This use case is greatly enhanced by the

provisioning of a 128-Kbyte private back-side CoreNet platform cache (CPC) for each e500mc core.

These caches can operate as a traditional unified cache, or be set to operate as Instruction Only, Data Only,

or even locked and used as memory-mapped SRAM.

CPU cores operating asymmetrically can be run at asynchronous clock rates. Each processor can source

its input clock from one of the multiple PLLs inside the P3041. This allows each core to operate at the

minimum frequency required to perform its assigned function, saving power. The cores are also capable

of running at half and quarter ratios of their input PLL frequency, and can switch between PLLs and ratios

nearly instantaneously. This allows lightly utilized CPUs to be slowed (under software control) for power

savings, rather than performing more complex task migration operations.

2.3

DPAA Multicore Processing Use Cases

Figure 3 shows several multicore processing use cases and the potential interaction with the Data Path

Acceleration Architecture (DPAA).